cpldfit: version O.87xd Xilinx Inc. Fitter Report Design Name: IC1 Date: 9-17-2014, 8:42AM Device Used: XC9536-7-VQ44 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 14 /36 ( 39%) 13 /180 ( 7%) 32 /72 ( 44%) 0 /36 ( 0%) 34 /34 (100%) ** Function Block Resources ** Function Mcells FB Inps Signals Pterms IO Block Used/Tot Used/Tot Used Used/Tot Used/Tot FB1 9/18 17/36 17 7/90 9/17 FB2 5/18 15/36 15 6/90 5/17 ----- ----- ----- ----- 14/36 32/72 13/180 14/34 * - Resource is exhausted ** Global Control Resources ** Global clock net(s) unused. Global output enable net(s) unused. Global set/reset net(s) unused. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 20 20 | I/O : 28 28 Output : 14 14 | GCK/IO : 3 3 Bidirectional : 0 0 | GTS/IO : 2 2 GCK : 0 0 | GSR/IO : 1 1 GTS : 0 0 | GSR : 0 0 | ---- ---- Total 34 34 ** Power Data ** There are 14 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). End of Mapped Resource Summary ************************** Errors and Warnings *************************** WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will use the default filename of 'IC1.ise'. ************************* Summary of Mapped Logic ************************ ** 14 Outputs ** Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State B_IRQ<1> 0 0 FB1_3 43 GCK/I/O O STD FAST B_NMI 0 0 FB1_5 44 GCK/I/O O STD FAST B_INT 1 1 FB1_6 2 I/O O STD FAST B_IRQ<0> 0 0 FB1_7 1 GCK/I/O O STD FAST JP5 1 1 FB1_13 12 I/O O STD FAST F_MEMRQ 2 12 FB1_14 13 I/O O STD FAST F_SIZ1 1 1 FB1_15 14 I/O O STD FAST F_IORQ 1 1 FB1_16 16 I/O O STD FAST F_SIZ0 1 1 FB1_17 18 I/O O STD FAST JP2 1 1 FB2_2 38 I/O O STD FAST B_WAIT 1 1 FB2_4 37 I/O O STD FAST JP3 1 1 FB2_5 34 GTS/I/O O STD FAST F_RESET 1 1 FB2_11 28 I/O O STD FAST JP4 2 12 FB2_17 19 I/O O STD FAST ** 20 Inputs ** Signal Loc Pin Pin Pin Name No. Type Use B_A<27> FB1_1 40 I/O I B_A<28> FB1_2 41 I/O I B_A<29> FB1_4 42 I/O I B_IORQ FB1_8 3 I/O I B_SIZ1 FB1_9 5 I/O I B_SIZ0 FB1_10 6 I/O I B_MEMRQ FB1_11 7 I/O I B_RESET FB1_12 8 I/O I B_A<26> FB2_1 39 I/O I B_A<25> FB2_3 36 GTS/I/O I B_A<24> FB2_6 33 GSR/I/O I B_A<23> FB2_7 32 I/O I B_A<22> FB2_8 31 I/O I B_A<21> FB2_9 30 I/O I B_A<20> FB2_10 29 I/O I F_WAIT FB2_12 27 I/O I F_NMI FB2_13 23 I/O I F_INT FB2_14 22 I/O I F_IRQ<0> FB2_15 21 I/O I F_IRQ<1> FB2_16 20 I/O I Legend: Pin No. - ~ - User Assigned ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. Pin No. - ~ - User Assigned *********************************** FB1 *********************************** Number of function block inputs used/remaining: 17/19 Number of signals used by logic mapping into function block: 17 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB1_1 40 I/O I (unused) 0 0 0 5 FB1_2 41 I/O I B_IRQ<1> 0 0 0 5 FB1_3 43 GCK/I/O O (unused) 0 0 0 5 FB1_4 42 I/O I B_NMI 0 0 0 5 FB1_5 44 GCK/I/O O B_INT 1 0 0 4 FB1_6 2 I/O O B_IRQ<0> 0 0 0 5 FB1_7 1 GCK/I/O O (unused) 0 0 0 5 FB1_8 3 I/O I (unused) 0 0 0 5 FB1_9 5 I/O I (unused) 0 0 0 5 FB1_10 6 I/O I (unused) 0 0 0 5 FB1_11 7 I/O I (unused) 0 0 0 5 FB1_12 8 I/O I JP5 1 0 0 4 FB1_13 12 I/O O F_MEMRQ 2 0 0 3 FB1_14 13 I/O O F_SIZ1 1 0 0 4 FB1_15 14 I/O O F_IORQ 1 0 0 4 FB1_16 16 I/O O F_SIZ0 1 0 0 4 FB1_17 18 I/O O (unused) 0 0 0 5 FB1_18 (b) Signals Used by Logic in Function Block 1: B_A<20> 7: B_A<26> 13: B_IORQ 2: B_A<21> 8: B_A<27> 14: B_SIZ0 3: B_A<22> 9: B_A<28> 15: B_SIZ1 4: B_A<23> 10: B_A<29> 16: F_NMI 5: B_A<24> 11: B_MEMRQ 17: F_IRQ<1> 6: B_A<25> 12: F_INT Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs B_IRQ<1> ........................................ 0 0 B_NMI ........................................ 0 0 B_INT ...........X............................ 1 1 B_IRQ<0> ........................................ 0 0 JP5 ................X....................... 1 1 F_MEMRQ XXXXXXXXXXX....X........................ 12 12 F_SIZ1 ..............X......................... 1 1 F_IORQ ............X........................... 1 1 F_SIZ0 .............X.......................... 1 1 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB2 *********************************** Number of function block inputs used/remaining: 15/21 Number of signals used by logic mapping into function block: 15 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB2_1 39 I/O I JP2 1 0 0 4 FB2_2 38 I/O O (unused) 0 0 0 5 FB2_3 36 GTS/I/O I B_WAIT 1 0 0 4 FB2_4 37 I/O O JP3 1 0 0 4 FB2_5 34 GTS/I/O O (unused) 0 0 0 5 FB2_6 33 GSR/I/O I (unused) 0 0 0 5 FB2_7 32 I/O I (unused) 0 0 0 5 FB2_8 31 I/O I (unused) 0 0 0 5 FB2_9 30 I/O I (unused) 0 0 0 5 FB2_10 29 I/O I F_RESET 1 0 0 4 FB2_11 28 I/O O (unused) 0 0 0 5 FB2_12 27 I/O I (unused) 0 0 0 5 FB2_13 23 I/O I (unused) 0 0 0 5 FB2_14 22 I/O I (unused) 0 0 0 5 FB2_15 21 I/O I (unused) 0 0 0 5 FB2_16 20 I/O I JP4 2 0 0 3 FB2_17 19 I/O O (unused) 0 0 0 5 FB2_18 (b) Signals Used by Logic in Function Block 1: B_A<20> 6: B_A<25> 11: B_MEMRQ 2: B_A<21> 7: B_A<26> 12: B_RESET 3: B_A<22> 8: B_A<27> 13: F_WAIT 4: B_A<23> 9: B_A<28> 14: F_IRQ<0> 5: B_A<24> 10: B_A<29> 15: F_NMI Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs JP2 .............X.......................... 1 1 B_WAIT ............X........................... 1 1 JP3 ..............X......................... 1 1 F_RESET ...........X............................ 1 1 JP4 XXXXXXXXXXX...X......................... 12 12 0----+----1----+----2----+----3----+----4 0 0 0 0 ******************************* Equations ******************************** ********** Mapped Logic ********** B_INT_I <= '0'; B_INT <= B_INT_I when B_INT_OE = '1' else 'Z'; B_INT_OE <= NOT F_INT; B_IRQ_I(0) <= '0'; B_IRQ(0) <= B_IRQ_I(0) when B_IRQ_OE(0) = '1' else 'Z'; B_IRQ_OE(0) <= '0'; B_IRQ_I(1) <= '0'; B_IRQ(1) <= B_IRQ_I(1) when B_IRQ_OE(1) = '1' else 'Z'; B_IRQ_OE(1) <= '0'; B_NMI_I <= '0'; B_NMI <= B_NMI_I when B_NMI_OE = '1' else 'Z'; B_NMI_OE <= '0'; B_WAIT_I <= '0'; B_WAIT <= B_WAIT_I when B_WAIT_OE = '1' else 'Z'; B_WAIT_OE <= NOT F_WAIT; F_IORQ <= B_IORQ; F_MEMRQ <= NOT (((NOT B_MEMRQ AND F_NMI AND B_A(21) AND B_A(20) AND B_A(22)) OR (NOT B_A(29) AND NOT B_A(28) AND NOT B_A(27) AND NOT B_A(26) AND NOT B_A(25) AND NOT B_A(24) AND NOT B_A(23) AND NOT B_MEMRQ AND B_A(21) AND B_A(20) AND B_A(22)))); F_RESET <= B_RESET; F_SIZ0 <= B_SIZ0; F_SIZ1 <= B_SIZ1; JP2 <= F_IRQ(0); JP3 <= F_NMI; JP4 <= ((NOT B_MEMRQ AND F_NMI AND B_A(21) AND B_A(20) AND B_A(22)) OR (NOT B_A(29) AND NOT B_A(28) AND NOT B_A(27) AND NOT B_A(26) AND NOT B_A(25) AND NOT B_A(24) AND NOT B_A(23) AND NOT B_MEMRQ AND B_A(21) AND B_A(20) AND B_A(22))); JP5 <= F_IRQ(1); Register Legend: FDCPE (Q,D,C,CLR,PRE); FTCPE (Q,D,C,CLR,PRE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC9536-7-VQ44 -------------------------------- /44 43 42 41 40 39 38 37 36 35 34 \ | 1 33 | | 2 32 | | 3 31 | | 4 30 | | 5 XC9536-7-VQ44 29 | | 6 28 | | 7 27 | | 8 26 | | 9 25 | | 10 24 | | 11 23 | \ 12 13 14 15 16 17 18 19 20 21 22 / -------------------------------- Pin Signal Pin Signal No. Name No. Name 1 B_IRQ<0> 23 F_NMI 2 B_INT 24 TDO 3 B_IORQ 25 GND 4 GND 26 VCC 5 B_SIZ1 27 F_WAIT 6 B_SIZ0 28 F_RESET 7 B_MEMRQ 29 B_A<20> 8 B_RESET 30 B_A<21> 9 TDI 31 B_A<22> 10 TMS 32 B_A<23> 11 TCK 33 B_A<24> 12 JP5 34 JP3 13 F_MEMRQ 35 VCC 14 F_SIZ1 36 B_A<25> 15 VCC 37 B_WAIT 16 F_IORQ 38 JP2 17 GND 39 B_A<26> 18 F_SIZ0 40 B_A<27> 19 JP4 41 B_A<28> 20 F_IRQ<1> 42 B_A<29> 21 F_IRQ<0> 43 B_IRQ<1> 22 F_INT 44 B_NMI Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc9536-7-VQ44 Optimization Method : DENSITY Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Power Mode : STD Ground on Unused IOs : OFF Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON FASTConnect/UIM optimzation : ON Local Feedback : ON Pin Feedback : ON Input Limit : 36 Pterm Limit : 25