#INFO: (ST-1216) Setting log file to 'D:/Projects/NDR/NDR2.0/CPLD/GDP_FPGA2.1/GDPFPGAII/hdldiagram_gen_hierarchy.html'. FileList::LoadDesign #-- (VHDL-1504) The default vhdl library search path is now "c:/program files/lscc/diamond/2.0/cae_library/vhdl_packages/vdbs" #-- (VHDL-1481) Analyzing VHDL file C:/Program Files/lscc/diamond/2.0/cae_library/synthesis/vhdl/xp.vhd #-- (VHDL-1493) Restoring VHDL parse-tree ieee.std_logic_1164 from c:/program files/lscc/diamond/2.0/cae_library/vhdl_packages/vdbs/ieee/std_logic_1164.vdb #-- (VHDL-1493) Restoring VHDL parse-tree std.standard from c:/program files/lscc/diamond/2.0/cae_library/vhdl_packages/vdbs/std/standard.vdb #-- (VHDL-1481) Analyzing VHDL file C:/Program Files/lscc/diamond/2.0/cae_library/synthesis/vhdl/xp.pkg #-- (VHDL-1481) Analyzing VHDL file D:/Projects/NDR/NDR2.0/CPLD/GDP_FPGA2.1/GDPFPGAII/vhdl/gdp_fpgaii_top.vhd #-- (VHDL-1493) Restoring VHDL parse-tree ieee.numeric_std from c:/program files/lscc/diamond/2.0/cae_library/vhdl_packages/vdbs/ieee/numeric_std.vdb #-- (VHDL-1493) Restoring VHDL parse-tree ieee.std_logic_arith from c:/program files/lscc/diamond/2.0/cae_library/vhdl_packages/vdbs/ieee/std_logic_arith.vdb #-- (VHDL-1493) Restoring VHDL parse-tree ieee.std_logic_unsigned from c:/program files/lscc/diamond/2.0/cae_library/vhdl_packages/vdbs/ieee/std_logic_unsigned.vdb #d:/projects/ndr/ndr2.0/cpld/gdp_fpga2.1/gdpfpgaii/vhdl/gdp_fpgaii_top.vhd(24,8-24,22) INFO: (VHDL-1012) analyzing entity gdp_fpgaii_top #d:/projects/ndr/ndr2.0/cpld/gdp_fpga2.1/gdpfpgaii/vhdl/gdp_fpgaii_top.vhd(132,14-132,17) INFO: (VHDL-1010) analyzing architecture rtl #-- (VHDL-1481) Analyzing VHDL file D:/Projects/NDR/NDR2.0/CPLD/GDP_FPGA2.1/GDPFPGAII/vhdl/nkc16_wb_wrapper.vhd #d:/projects/ndr/ndr2.0/cpld/gdp_fpga2.1/gdpfpgaii/vhdl/nkc16_wb_wrapper.vhd(22,8-22,24) INFO: (VHDL-1012) analyzing entity nkc16_wb_wrapper #d:/projects/ndr/ndr2.0/cpld/gdp_fpga2.1/gdpfpgaii/vhdl/nkc16_wb_wrapper.vhd(62,14-62,17) INFO: (VHDL-1010) analyzing architecture rtl #-- (VHDL-1481) Analyzing VHDL file D:/Projects/NDR/NDR2.0/CPLD/GDP_FPGA2.1/GDPFPGAII/vhdl/gdp_intercon.vhd #d:/projects/ndr/ndr2.0/cpld/gdp_fpga2.1/gdpfpgaii/vhdl/gdp_intercon.vhd(17,8-17,23) INFO: (VHDL-1012) analyzing entity wb_interconnect #d:/projects/ndr/ndr2.0/cpld/gdp_fpga2.1/gdpfpgaii/vhdl/gdp_intercon.vhd(64,14-64,22) INFO: (VHDL-1010) analyzing architecture intercon #-- (VHDL-1481) Analyzing VHDL file D:/Projects/NDR/NDR2.0/CPLD/GDP_FPGA2.1/GDPFPGAII/vhdl/sram.vhd #d:/projects/ndr/ndr2.0/cpld/gdp_fpga2.1/gdpfpgaii/vhdl/sram.vhd(17,8-17,12) INFO: (VHDL-1012) analyzing entity sram #d:/projects/ndr/ndr2.0/cpld/gdp_fpga2.1/gdpfpgaii/vhdl/sram.vhd(48,14-48,20) INFO: (VHDL-1010) analyzing architecture sram_1 #--Elaborating Design #d:/projects/ndr/ndr2.0/cpld/gdp_fpga2.1/gdpfpgaii/vhdl/gdp_fpgaii_top.vhd(24,8-24,22) INFO: (VHDL-1067) elaborating gdp_fpgaii_top(rtl) #d:/projects/ndr/ndr2.0/cpld/gdp_fpga2.1/gdpfpgaii/vhdl/gdp_fpgaii_top.vhd(319,3-319,39) -- (VHDL-1549) expression has 25 elements ; formal wbm_address expects 20 #d:/projects/ndr/ndr2.0/cpld/gdp_fpga2.1/gdpfpgaii/vhdl/nkc16_wb_wrapper.vhd(22,8-22,24) INFO: (VHDL-1067) elaborating nkc16_wb_wrapper(RTL) #d:/projects/ndr/ndr2.0/cpld/gdp_fpga2.1/gdpfpgaii/vhdl/gdp_intercon.vhd(17,8-17,23) INFO: (VHDL-1067) elaborating wb_interconnect(intercon) #d:/projects/ndr/ndr2.0/cpld/gdp_fpga2.1/gdpfpgaii/vhdl/sram.vhd(17,8-17,12) INFO: (VHDL-1067) elaborating sram(sram_1) #-- (ST-1001) Root modules/entities/cells (1): #-- gdp_fpgaii_top #Design load finished with (0) errors, and (0) warnings.