PAR: Place And Route Diamond (64-bit) 2.0.1.184. Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2012 Lattice Semiconductor Corporation, All rights reserved. Tue Feb 24 14:41:53 2015 C:/Program Files/Lattice/Diamond2.0/diamond/2.0/ispfpga\bin\nt64\par -f GDPFPGAII_GDPFPGAII.p2t GDPFPGAII_GDPFPGAII_map.ncd GDPFPGAII_GDPFPGAII.dir GDPFPGAII_GDPFPGAII.prf Preference file: GDPFPGAII_GDPFPGAII.prf. Cost Table Summary Level/ Number Timing Run NCD Cost [ncd] Unrouted Score Time Status ---------- -------- -------- ----- ------------ 5_1 * 0 0 30 Complete * : Design saved. par done! Lattice Place and Route Report for Design "GDPFPGAII_GDPFPGAII_map.ncd" Tue Feb 24 14:41:53 2015 Best Par Run PAR: Place And Route Diamond (64-bit) 2.0.1.184. Command Line: C:/Program Files/Lattice/Diamond2.0/diamond/2.0/ispfpga\bin\nt64\par -f GDPFPGAII_GDPFPGAII.p2t GDPFPGAII_GDPFPGAII_map.ncd GDPFPGAII_GDPFPGAII.dir GDPFPGAII_GDPFPGAII.prf Preference file: GDPFPGAII_GDPFPGAII.prf. Placement level-cost: 5-1. Routing Iterations: 6 Loading design for application par from file GDPFPGAII_GDPFPGAII_map.ncd. Design name: gdp_fpgaii_top NCD version: 3.2 Vendor: LATTICE Device: LFXP6C Package: PQFP208 Performance: 5 Loading device for application par from file 'mg5g27x32.nph' in environment C:/Program Files/Lattice/Diamond2.0/diamond/2.0/ispfpga. loading NP_PATTERN_MANAGER end NP_PATTERN_MANAGER Package Status: Final Version 1.27 Performance Hardware Data Status: Version 1.227 License checked out. Ignore Preference Error(s): True Device utilization summary: GSR 1/1 100% used IOLOGIC 46/216 21% used PIO (prelim) 140/188 74% used 140/142 98% bonded EBR 2/8 25% used SLICE 1944/2880 67% used Number of Signals: 4622 Number of Connections: 14125 Pin Constraint Summary: 139 out of 139 pins locked (100% locked). The following 2 signals are selected to use the primary clock routing resources: clk_i_c (driver: clk_i, clk load #: 842) GDPHS.GDP.vram.mstate_c[2] (driver: GDPHS/GDP/vram/SLICE_1415, clk load #: 24) No signal is selected as DCS clock. The following 2 signals are selected to use the secondary clock routing resources: reset_n_i_c (driver: reset_n_i, clk load #: 0, sr load #: 43, ce load #: 0) GDPHS/impl_mouse.mouse/un7_en_i (driver: SLICE_1252, clk load #: 0, sr load #: 0, ce load #: 20) Signal GDPHS/reset_n is selected as Global Set/Reset. . Starting Placer Phase 0. .......... Finished Placer Phase 0. REAL time: 6 secs Starting Placer Phase 1. ......................... Placer score = 908721. Finished Placer Phase 1. REAL time: 15 secs Starting Placer Phase 2. . Placer score = 899619 Finished Placer Phase 2. REAL time: 16 secs Clock Report Global Clock Resources: CLK_PIN : 1 out of 4 (25%) PLL : 0 out of 2 (0%) Quadrants All (TL, TR, BL, BR) - Global Clocks: PRIMARY "clk_i_c" from comp "clk_i" on CLK_PIN site "31 (PL17A)", clk load = 842 PRIMARY "GDPHS.GDP.vram.mstate_c[2]" from F1 on comp "GDPHS/GDP/vram/SLICE_1415" on site "R15C2C", clk load = 24 SECONDARY "reset_n_i_c" from comp "reset_n_i" on PIO site "11 (PL4A)", clk load = 0, ce load = 0, sr load = 43 SECONDARY "GDPHS/impl_mouse.mouse/un7_en_i" from F0 on comp "SLICE_1252" on site "R2C17A", clk load = 0, ce load = 20, sr load = 0 PRIMARY : 2 out of 4 (50%) DCS : 0 out of 2 (0%) SECONDARY: 2 out of 4 (50%) I/O Usage Summary (final): 140 out of 188 (74.5%) PIO sites used. 140 out of 142 (98.6%) bonded PIO sites used. Number of PIO comps: 140; differential: 0 Number of Vref pins used: 0 I/O Bank Usage Summary: +----------+----------------+------------+------------+------------+ | I/O Bank | Usage | Bank Vccio | Bank Vref1 | Bank Vref2 | +----------+----------------+------------+------------+------------+ | 0 | 20 / 20 (100%) | 3.3V | - | - | | 1 | 18 / 18 (100%) | 3.3V | - | - | | 2 | 16 / 17 ( 94%) | - | - | - | | 3 | 14 / 14 (100%) | 3.3V | - | - | | 4 | 21 / 21 (100%) | 3.3V | - | - | | 5 | 21 / 21 (100%) | 3.3V | - | - | | 6 | 16 / 17 ( 94%) | 3.3V | - | - | | 7 | 14 / 14 (100%) | 3.3V | - | - | +----------+----------------+------------+------------+------------+ Total placer CPU time: 16 secs Dumping design to file GDPFPGAII_GDPFPGAII.dir/5_1.ncd. 0 connections routed; 14125 unrouted. Starting router resource preassignment WARNING - par: The driver of secondary clock net reset_n_i_c is not placed on one of the PIO sites dedicated for secondary clocks. This secondary clock will be routed through general routing resource and may suffer from excessive delay or skew. Completed router resource preassignment. Real time: 23 secs Start NBR router at 14:42:16 02/24/15 ***************************************************************** Info: NBR allows conflicts(one node used by more than one signal) in the earlier iterations. In each iteration, it tries to solve the conflicts while keeping the critical connections routed as shorter as possible. The routing process is said to be completed when no conflicts exist and all connections are routed. Note: NBR uses a different method to calculate timing slacks. The worst slack and total negative slack may not be the same as that in TRCE report. You should always run TRCE to verify your design. Thanks. ***************************************************************** Start NBR special constraint process at 14:42:16 02/24/15 Start NBR section for initial routing Level 1, iteration 1 0(0.00%) conflict; 12118(85.79%) untouched conns; 0 (nbr) score; Estimated worst slack/total negative slack: 10.455ns/0.000ns; real time: 24 secs Level 4, iteration 1 847(0.34%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 8.274ns/0.000ns; real time: 26 secs Info: Initial congestion level at 75% usage is 0 Info: Initial congestion area at 75% usage is 0 (0.00%) Start NBR section for normal routing Level 4, iteration 1 461(0.19%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 8.939ns/0.000ns; real time: 26 secs Level 4, iteration 2 167(0.07%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 8.850ns/0.000ns; real time: 27 secs Level 4, iteration 3 59(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 8.850ns/0.000ns; real time: 27 secs Level 4, iteration 4 26(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 8.850ns/0.000ns; real time: 27 secs Level 4, iteration 5 5(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 8.850ns/0.000ns; real time: 28 secs Level 4, iteration 6 3(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 8.850ns/0.000ns; real time: 28 secs Level 4, iteration 7 1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 8.850ns/0.000ns; real time: 28 secs Level 4, iteration 8 1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 8.850ns/0.000ns; real time: 28 secs Level 4, iteration 9 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack: 8.850ns/0.000ns; real time: 28 secs Start NBR section for post-routing Dumping design to file GDPFPGAII_GDPFPGAII.dir/5_1.ncd. End NBR router with 0 unrouted connection NBR Summary ----------- Number of unrouted connections : 0 (0.00%) Number of connections with timing violations : 0 (0.00%) Estimated worst slack : 8.850ns Timing score : 0 ----------- Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. Total CPU time 28 secs Total REAL time: 29 secs Completely routed. End of route. 14125 routed (100.00%); 0 unrouted. Checking DRC ... No errors found. Timing score: 0 Total REAL time to completion: 30 secs Dumping design to file GDPFPGAII_GDPFPGAII.dir/5_1.ncd. All signals are completely routed. par done! Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2012 Lattice Semiconductor Corporation, All rights reserved.