#Build: Synplify Pro F-2012.03L-1 , Build 063R, May 17 2012 #install: C:\Program Files\lscc\diamond\2.0\synpbase #OS: Windows 7 6.1 #Hostname: SYNWM9582WM1 #Implementation: GDPFPGAII $ Start of Compile #Fri Oct 10 21:51:20 2014 Synopsys VHDL Compiler, version comp201203rcp1, Build 061R, built May 17 2012 @N: : | Running in 64-bit mode Copyright (C) 1994-2012 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc. @N:CD720 : std.vhd(123) | Setting time resolution to ns @N: : gdp_fpgaii_top.vhd(25) | Top entity is set to gdp_fpgaii_top. VHDL syntax check successful! @N:CD630 : gdp_fpgaii_top.vhd(25) | Synthesizing work.gdp_fpgaii_top.rtl @W:CD638 : gdp_fpgaii_top.vhd(495) | Signal debug_sig is undriven @N:CD630 : sram.vhd(17) | Synthesizing work.sram.sram_1 Post processing for work.sram.sram_1 @W:CL169 : sram.vhd(64) | Pruning register ws_cnt(20 downto 0) @N:CD630 : gide.vhd(26) | Synthesizing work.gide.behavioral @N:CD231 : gide.vhd(75) | Using onehot encoding for type state_type (init="100000000000000000000000000000000000") Post processing for work.gide.behavioral @W:CL271 : gide.vhd(94) | Pruning bits 4 to 2 of q(4 downto 0) -- not in use ... @A:CL282 : gide.vhd(127) | Feedback mux created for signal gide_wbs_ack -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @N:CD630 : gdp_lattice_top.vhd(27) | Synthesizing work.gdp_lattice_top.rtl @N:CD367 : gdp_lattice_top.vhd(548) | Instance GDP, Port monitoring_o, Bit <1> connection not specified @N:CD367 : gdp_lattice_top.vhd(548) | Instance GDP, Port monitoring_o, Bit <2> connection not specified @N:CD367 : gdp_lattice_top.vhd(548) | Instance GDP, Port monitoring_o, Bit <3> connection not specified @N:CD367 : gdp_lattice_top.vhd(548) | Instance GDP, Port monitoring_o, Bit <4> connection not specified @N:CD367 : gdp_lattice_top.vhd(548) | Instance GDP, Port monitoring_o, Bit <5> connection not specified @N:CD367 : gdp_lattice_top.vhd(548) | Instance GDP, Port monitoring_o, Bit <6> connection not specified @N:CD367 : gdp_lattice_top.vhd(548) | Instance GDP, Port monitoring_o, Bit <7> connection not specified @N:CD367 : gdp_lattice_top.vhd(548) | Instance GDP, Port monitoring_o, Bit <8> connection not specified @N:CD367 : gdp_lattice_top.vhd(548) | Instance GDP, Port monitoring_o, Bit <9> connection not specified @N:CD367 : gdp_lattice_top.vhd(548) | Instance GDP, Port monitoring_o, Bit <10> connection not specified @N:CD367 : gdp_lattice_top.vhd(548) | Instance GDP, Port monitoring_o, Bit <11> connection not specified @N:CD367 : gdp_lattice_top.vhd(548) | Instance GDP, Port monitoring_o, Bit <12> connection not specified @N:CD367 : gdp_lattice_top.vhd(548) | Instance GDP, Port monitoring_o, Bit <13> connection not specified @N:CD367 : gdp_lattice_top.vhd(548) | Instance GDP, Port monitoring_o, Bit <14> connection not specified @N:CD367 : gdp_lattice_top.vhd(548) | Instance GDP, Port monitoring_o, Bit <15> connection not specified @W:CD638 : gdp_lattice_top.vhd(423) | Signal busyrx is undriven @W:CD638 : gdp_lattice_top.vhd(424) | Signal doutparrx is undriven @W:CD638 : gdp_lattice_top.vhd(425) | Signal datavalidrx is undriven @W:CD638 : gdp_lattice_top.vhd(426) | Signal olddatavalidrx is undriven @W:CD638 : gdp_lattice_top.vhd(442) | Signal vdip_cs is undriven @W:CD638 : gdp_lattice_top.vhd(443) | Signal vdip_data is undriven @W:CD638 : gdp_lattice_top.vhd(452) | Signal q is undriven @N:CD630 : Timer.vhd(21) | Synthesizing work.timer.rtl Post processing for work.timer.rtl @W:CL271 : Timer.vhd(77) | Pruning bits 5 to 3 of ctrl_reg(7 downto 0) -- not in use ... @N:CD630 : SPI_Interface.vhd(21) | Synthesizing work.spi_interface.rtl Post processing for work.spi_interface.rtl @W:CL265 : SPI_Interface.vhd(94) | Pruning bit 4 of ctrl_reg(7 downto 0) -- not in use ... @N:CD630 : wf2149ip_top_soc.vhd(20) | Synthesizing work.wf2149ip_top_soc.structure @N:CD233 : wf2149ip_pkg.vhd(20) | Using sequential encoding for type buscycles_t @N:CD630 : wf2149ip_wave.vhd(21) | Synthesizing work.wf2149ip_wave.behavior @N:CD233 : wf2149ip_pkg.vhd(20) | Using sequential encoding for type buscycles_t @N:CD630 : dac.vhd(28) | Synthesizing work.dac.rtl Post processing for work.dac.rtl Post processing for work.wf2149ip_wave.behavior @A:CL282 : wf2149ip_wave.vhd(76) | Feedback mux created for signal ENV_RESET -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. Post processing for work.wf2149ip_top_soc.structure @A:CL282 : wf2149ip_top_soc.vhd(67) | Feedback mux created for signal WAV_STRB -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @N:CD630 : Ser1.vhd(23) | Synthesizing work.ser1.rtl @N:CD233 : Ser1.vhd(73) | Using sequential encoding for type tx_state_t @N:CD233 : Ser1.vhd(106) | Using sequential encoding for type rx_state_t @W:CD604 : Ser1.vhd(414) | OTHERS clause is not synthesized @W:CD604 : Ser1.vhd(562) | OTHERS clause is not synthesized @N:CD630 : InputSync-e.vhd(15) | Synthesizing work.inputsync.rtl Post processing for work.inputsync.rtl @N:CD630 : InputSync-e.vhd(15) | Synthesizing work.inputsync.rtl Post processing for work.inputsync.rtl Post processing for work.ser1.rtl @W:CL190 : Ser1.vhd(196) | Optimizing register bit Status_reg(5) to a constant 0 @W:CL190 : Ser1.vhd(196) | Optimizing register bit Status_reg(7) to a constant 0 @W:CL260 : Ser1.vhd(196) | Pruning register bit 7 of Status_reg(7 downto 0) @W:CL260 : Ser1.vhd(196) | Pruning register bit 5 of Status_reg(7 downto 0) @N:CD630 : PS2Mouse.vhd(28) | Synthesizing work.ps2mouse.rtl @N:CD233 : PS2Mouse.vhd(88) | Using sequential encoding for type mouse_state_t @N:CD233 : PS2Mouse.vhd(89) | Using sequential encoding for type mouse_send_state_t @W:CD604 : PS2Mouse.vhd(241) | OTHERS clause is not synthesized @W:CD604 : PS2Mouse.vhd(277) | OTHERS clause is not synthesized @W:CD604 : PS2Mouse.vhd(280) | OTHERS clause is not synthesized @N:CD630 : PS2_Interface.vhd(28) | Synthesizing work.ps2_interface.rtl @N:CD233 : PS2_Interface.vhd(67) | Using sequential encoding for type ps2direction_t @N:CD231 : PS2_Interface.vhd(68) | Using onehot encoding for type state_t (idle="10000") @N:CD233 : PS2_Interface.vhd(69) | Using sequential encoding for type clkedge_t Post processing for work.ps2_interface.rtl Post processing for work.ps2mouse.rtl @W:CL279 : PS2Mouse.vhd(287) | Pruning register bits 7 to 6 of button_stat(7 downto 0) @N:CD630 : PS2Keyboard.vhd(28) | Synthesizing work.ps2keyboard.rtl @N:CD233 : PS2Keyboard.vhd(118) | Using sequential encoding for type fifordstate_t @N:CD233 : PS2Keyboard.vhd(120) | Using sequential encoding for type kbd_init_state_t @N:CD233 : PS2Keyboard.vhd(121) | Using sequential encoding for type kbd_send_state_t @W:CD604 : PS2Keyboard.vhd(435) | OTHERS clause is not synthesized @W:CD604 : PS2Keyboard.vhd(438) | OTHERS clause is not synthesized @W:CD604 : PS2Keyboard.vhd(527) | OTHERS clause is not synthesized @W:CD604 : PS2Keyboard.vhd(553) | OTHERS clause is not synthesized @W:CD604 : PS2Keyboard.vhd(556) | OTHERS clause is not synthesized @N:CD630 : ps2_fifo.vhd(15) | Synthesizing work.ps2_fifo.structure @N:CD630 : xp.vhd(1549) | Synthesizing work.rom16x1.syn_black_box Post processing for work.rom16x1.syn_black_box @N:CD630 : xp.vhd(542) | Synthesizing work.fd1p3dx.syn_black_box Post processing for work.fd1p3dx.syn_black_box @N:CD630 : xp.vhd(662) | Synthesizing work.fd1s3bx.syn_black_box Post processing for work.fd1s3bx.syn_black_box @N:CD630 : xp.vhd(673) | Synthesizing work.fd1s3dx.syn_black_box Post processing for work.fd1s3dx.syn_black_box @N:CD630 : xp.vhd(384) | Synthesizing work.dpr16x2b.syn_black_box Post processing for work.dpr16x2b.syn_black_box @N:CD630 : xp.vhd(1643) | Synthesizing work.vlo.syn_black_box Post processing for work.vlo.syn_black_box @N:CD630 : xp.vhd(346) | Synthesizing work.cu2.syn_black_box Post processing for work.cu2.syn_black_box @N:CD630 : xp.vhd(1635) | Synthesizing work.vhi.syn_black_box Post processing for work.vhi.syn_black_box @N:CD630 : xp.vhd(212) | Synthesizing work.ageb2.syn_black_box Post processing for work.ageb2.syn_black_box @N:CD630 : xp.vhd(471) | Synthesizing work.fadd2.syn_black_box Post processing for work.fadd2.syn_black_box @N:CD630 : xp.vhd(224) | Synthesizing work.aleb2.syn_black_box Post processing for work.aleb2.syn_black_box @N:CD630 : xp.vhd(186) | Synthesizing work.cb2.syn_black_box Post processing for work.cb2.syn_black_box @N:CD630 : xp.vhd(236) | Synthesizing work.and2.syn_black_box Post processing for work.and2.syn_black_box @N:CD630 : xp.vhd(989) | Synthesizing work.inv.syn_black_box Post processing for work.inv.syn_black_box @N:CD630 : xp.vhd(1711) | Synthesizing work.xor2.syn_black_box Post processing for work.xor2.syn_black_box Post processing for work.ps2_fifo.structure @W:CL168 : ps2_fifo.vhd(316) | Pruning instance r_ctr_1 -- not in use ... @W:CL168 : ps2_fifo.vhd(305) | Pruning instance w_ctr_1 -- not in use ... @W:CL168 : ps2_fifo.vhd(236) | Pruning instance FF_7 -- not in use ... @W:CL168 : ps2_fifo.vhd(224) | Pruning instance FF_10 -- not in use ... @N:CD630 : PS2_Decoder.vhd(20) | Synthesizing work.ps2_decoder.rtl @N:CD233 : PS2_Decoder.vhd(42) | Using sequential encoding for type fetch_state_t @W:CD604 : PS2_Decoder.vhd(528) | OTHERS clause is not synthesized Post processing for work.ps2_decoder.rtl @W:CL190 : PS2_Decoder.vhd(538) | Optimizing register bit KeyStates(1) to a constant 0 @W:CL260 : PS2_Decoder.vhd(538) | Pruning register bit 1 of KeyStates(7 downto 0) Post processing for work.ps2keyboard.rtl @A:CL282 : PS2Keyboard.vhd(446) | Feedback mux created for signal DataOut_o[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @W:CL111 : PS2Keyboard.vhd(446) | All reachable assignments to KeyOptsReg(2) assign '0'; register removed by optimization @W:CL111 : PS2Keyboard.vhd(446) | All reachable assignments to KeyOptsReg(3) assign '0'; register removed by optimization @W:CL111 : PS2Keyboard.vhd(446) | All reachable assignments to KeyOptsReg(4) assign '0'; register removed by optimization @W:CL111 : PS2Keyboard.vhd(446) | All reachable assignments to KeyOptsReg(5) assign '0'; register removed by optimization @W:CL111 : PS2Keyboard.vhd(446) | All reachable assignments to KeyOptsReg(6) assign '0'; register removed by optimization @N:CD630 : gdp_top.vhd(25) | Synthesizing work.gdp_top.rtl @N:CD367 : gdp_top.vhd(228) | Instance video, Port monitoring_o, Bit <1> connection not specified @N:CD367 : gdp_top.vhd(228) | Instance video, Port monitoring_o, Bit <2> connection not specified @N:CD367 : gdp_top.vhd(228) | Instance video, Port monitoring_o, Bit <3> connection not specified @N:CD367 : gdp_top.vhd(228) | Instance video, Port monitoring_o, Bit <4> connection not specified @N:CD367 : gdp_top.vhd(228) | Instance video, Port monitoring_o, Bit <5> connection not specified @N:CD367 : gdp_top.vhd(228) | Instance video, Port monitoring_o, Bit <6> connection not specified @N:CD367 : gdp_top.vhd(228) | Instance video, Port monitoring_o, Bit <7> connection not specified @W:CD326 : gdp_top.vhd(336) | Port rom_ena_o of entity work.gdp_vram is unconnected @W:CD796 : gdp_top.vhd(182) | Bit 1 of signal monitoring is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. @W:CD796 : gdp_top.vhd(182) | Bit 2 of signal monitoring is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. @W:CD796 : gdp_top.vhd(182) | Bit 3 of signal monitoring is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. @W:CD796 : gdp_top.vhd(182) | Bit 4 of signal monitoring is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. @W:CD796 : gdp_top.vhd(182) | Bit 5 of signal monitoring is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. @W:CD796 : gdp_top.vhd(182) | Bit 6 of signal monitoring is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. @W:CD796 : gdp_top.vhd(182) | Bit 7 of signal monitoring is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. @W:CD796 : gdp_top.vhd(182) | Bit 8 of signal monitoring is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. @W:CD796 : gdp_top.vhd(182) | Bit 9 of signal monitoring is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. @W:CD796 : gdp_top.vhd(182) | Bit 10 of signal monitoring is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. @W:CD796 : gdp_top.vhd(182) | Bit 11 of signal monitoring is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. @W:CD796 : gdp_top.vhd(182) | Bit 12 of signal monitoring is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. @W:CD796 : gdp_top.vhd(182) | Bit 13 of signal monitoring is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. @W:CD796 : gdp_top.vhd(182) | Bit 14 of signal monitoring is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. @W:CD796 : gdp_top.vhd(182) | Bit 15 of signal monitoring is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. @N:CD630 : gdp_vram.vhd(22) | Synthesizing work.gdp_vram.rtl @N:CD233 : gdp_vram.vhd(62) | Using sequential encoding for type state_t @W:CD604 : gdp_vram.vhd(190) | OTHERS clause is not synthesized @W:CD434 : gdp_vram.vhd(87) | Signal ram_address in the sensitivity list is not used in the process @W:CD434 : gdp_vram.vhd(87) | Signal wr_data in the sensitivity list is not used in the process @W:CD434 : gdp_vram.vhd(87) | Signal rd_data in the sensitivity list is not used in the process @W:CD434 : gdp_vram.vhd(87) | Signal ram_wren in the sensitivity list is not used in the process @W:CD434 : gdp_vram.vhd(88) | Signal kernel_data in the sensitivity list is not used in the process @W:CD434 : gdp_vram.vhd(89) | Signal chr_rom_addr_i in the sensitivity list is not used in the process @W:CD434 : gdp_vram.vhd(89) | Signal rom_data in the sensitivity list is not used in the process @W:CD638 : gdp_vram.vhd(77) | Signal srom_en is undriven @W:CD638 : gdp_vram.vhd(79) | Signal srom_req_pend is undriven @W:CD638 : gdp_vram.vhd(80) | Signal srom_data is undriven Post processing for work.gdp_vram.rtl @N:CD630 : gdp_kernel.vhd(22) | Synthesizing work.gdp_kernel.rtl @N:CD231 : gdp_kernel.vhd(178) | Using onehot encoding for type state_t (idle_e="10000") @N:CD231 : gdp_global-p.vhd(57) | Using onehot encoding for type drawcmd_t (idle_e="10000") @W:CD604 : gdp_kernel.vhd(603) | OTHERS clause is not synthesized @N:CD630 : gdp_character.vhd(21) | Synthesizing work.gdp_character.rtl @N:CD233 : gdp_character.vhd(105) | Using sequential encoding for type char_state_t @W:CD604 : gdp_character.vhd(446) | OTHERS clause is not synthesized @W:CD434 : gdp_character.vhd(271) | Signal rom_busy_i in the sensitivity list is not used in the process @W:CD434 : gdp_character.vhd(271) | Signal rom_ena in the sensitivity list is not used in the process @N:CD630 : gdp_font_ram.vhd(8) | Synthesizing work.gdp_font_ram.rtl Post processing for work.gdp_font_ram.rtl @N:CL134 : gdp_font_ram.vhd(23) | Found RAM iram, depth=1024, width=8 Post processing for work.gdp_character.rtl @W:CL169 : gdp_character.vhd(198) | Pruning register finished @W:CL169 : gdp_character.vhd(198) | Pruning register rom_ena @N:CD630 : gdp_bresenham.vhd(21) | Synthesizing work.gdp_bresenham.rtl @N:CD231 : gdp_bresenham.vhd(72) | Using onehot encoding for type bres_state_t (idle_e="10000") Post processing for work.gdp_bresenham.rtl @W:CL190 : gdp_bresenham.vhd(133) | Optimizing register bit edec(0) to a constant 0 @W:CL190 : gdp_bresenham.vhd(133) | Optimizing register bit einc(0) to a constant 0 @W:CL260 : gdp_bresenham.vhd(133) | Pruning register bit 0 of einc(10 downto 0) @W:CL260 : gdp_bresenham.vhd(133) | Pruning register bit 0 of edec(10 downto 0) @N:CD630 : gdp_decoder.vhd(22) | Synthesizing work.gdp_decoder.rtl @N:CD231 : gdp_global-p.vhd(57) | Using onehot encoding for type drawcmd_t (idle_e="10000") Post processing for work.gdp_decoder.rtl Post processing for work.gdp_kernel.rtl @N:CD630 : gdp_video.vhd(23) | Synthesizing work.gdp_video.rtl @N:CD233 : gdp_video.vhd(87) | Using sequential encoding for type rd_state_t @W:CD604 : gdp_video.vhd(279) | OTHERS clause is not synthesized @W:CD434 : gdp_video.vhd(218) | Signal rd_address in the sensitivity list is not used in the process @W:CD434 : gdp_video.vhd(219) | Signal rd_ack_i in the sensitivity list is not used in the process @N:CD630 : gdp_clut.vhd(22) | Synthesizing work.gdp_clut.rtl Post processing for work.gdp_clut.rtl Post processing for work.gdp_video.rtl @A:CL282 : gdp_video.vhd(155) | Feedback mux created for signal isCursor -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. Post processing for work.gdp_top.rtl @N:CD630 : gdp_bi.vhd(22) | Synthesizing work.gdp_bi.rtl @N:CD630 : InputSync-e.vhd(15) | Synthesizing work.inputsync.rtl Post processing for work.inputsync.rtl Post processing for work.gdp_bi.rtl Post processing for work.gdp_lattice_top.rtl @W:CL252 : gdp_lattice_top.vhd(443) | Bit 0 of signal vdip_data is floating -- simulation mismatch possible. @W:CL252 : gdp_lattice_top.vhd(443) | Bit 1 of signal vdip_data is floating -- simulation mismatch possible. @W:CL252 : gdp_lattice_top.vhd(443) | Bit 2 of signal vdip_data is floating -- simulation mismatch possible. @W:CL252 : gdp_lattice_top.vhd(443) | Bit 3 of signal vdip_data is floating -- simulation mismatch possible. @W:CL252 : gdp_lattice_top.vhd(443) | Bit 4 of signal vdip_data is floating -- simulation mismatch possible. @W:CL252 : gdp_lattice_top.vhd(443) | Bit 5 of signal vdip_data is floating -- simulation mismatch possible. @W:CL252 : gdp_lattice_top.vhd(443) | Bit 6 of signal vdip_data is floating -- simulation mismatch possible. @W:CL252 : gdp_lattice_top.vhd(443) | Bit 7 of signal vdip_data is floating -- simulation mismatch possible. @W:CL240 : gdp_lattice_top.vhd(442) | vdip_cs is not assigned a value (floating) -- simulation mismatch possible. @W:CL169 : gdp_lattice_top.vhd(458) | Pruning register shreg(9 downto 0) @N:CD630 : gdp_intercon.vhd(18) | Synthesizing work.wb_interconnect.intercon @N:CD233 : gdp_intercon.vhd(170) | Using sequential encoding for type state_type @W:CD434 : gdp_intercon.vhd(376) | Signal sys_clk_i in the sensitivity list is not used in the process @W:CD434 : gdp_intercon.vhd(376) | Signal sys_reset_n_i in the sensitivity list is not used in the process @W:CD434 : gdp_intercon.vhd(376) | Signal gdphs_sram_cs in the sensitivity list is not used in the process @W:CD434 : gdp_intercon.vhd(376) | Signal gdphs_wbm_strobe in the sensitivity list is not used in the process @W:CD434 : gdp_intercon.vhd(376) | Signal gdphs_wbm_cycle in the sensitivity list is not used in the process @W:CD434 : gdp_intercon.vhd(376) | Signal hsync_i in the sensitivity list is not used in the process @W:CD434 : gdp_intercon.vhd(376) | Signal vsync_i in the sensitivity list is not used in the process @W:CG296 : gdp_intercon.vhd(376) | Incomplete sensitivity list - assuming completeness @W:CG290 : gdp_intercon.vhd(378) | Referenced variable black_i is not in sensitivity list @W:CD638 : gdp_intercon.vhd(171) | Signal state is undriven @W:CD638 : gdp_intercon.vhd(171) | Signal next_state is undriven Post processing for work.wb_interconnect.intercon @W:CL240 : gdp_intercon.vhd(31) | IRQ1_o is not assigned a value (floating) -- simulation mismatch possible. @W:CL240 : gdp_intercon.vhd(30) | IRQ0_o is not assigned a value (floating) -- simulation mismatch possible. @W:CL111 : gdp_intercon.vhd(207) | All reachable assignments to vdip_cs assign '0'; register removed by optimization @W:CL117 : gdp_intercon.vhd(473) | Latch generated from process for signal sram_buffer(15 downto 0); possible missing assignment in an if or case statement. @N:CD630 : nkc16_wb_wrapper.vhd(25) | Synthesizing work.nkc16_wb_wrapper.rtl @W:CD434 : nkc16_wb_wrapper.vhd(292) | Signal strobe in the sensitivity list is not used in the process @W:CG296 : nkc16_wb_wrapper.vhd(292) | Incomplete sensitivity list - assuming completeness @W:CG290 : nkc16_wb_wrapper.vhd(297) | Referenced variable fpga_en is not in sensitivity list Post processing for work.nkc16_wb_wrapper.rtl @W:CL240 : nkc16_wb_wrapper.vhd(61) | debug_o is not assigned a value (floating) -- simulation mismatch possible. Post processing for work.gdp_fpgaii_top.rtl @W:CL159 : gdp_intercon.vhd(63) | Input Hsync_i is unused @W:CL159 : gdp_intercon.vhd(64) | Input Vsync_i is unused @N:CL201 : gdp_video.vhd(289) | Trying to extract state machine for register rd_state Extracted state machine for register rd_state State machine has 4 reachable states with original encodings of: 00 01 10 11 @W:CL247 : gdp_video.vhd(52) | Input port bit 11 of cx1_i(11 downto 0) is unused @W:CL247 : gdp_video.vhd(53) | Input port bit 11 of cx2_i(11 downto 0) is unused @W:CL247 : gdp_video.vhd(54) | Input port bit 11 of cy1_i(11 downto 0) is unused @W:CL247 : gdp_video.vhd(55) | Input port bit 11 of cy2_i(11 downto 0) is unused @W:CL157 : gdp_video.vhd(140) | Output monitoring_o has undriven bits -- simulation mismatch possible. @W:CL159 : gdp_video.vhd(33) | Input rd_ack_i is unused @N:CL201 : gdp_decoder.vhd(188) | Trying to extract state machine for register drawCmd Extracted state machine for register drawCmd State machine has 5 reachable states with original encodings of: 00001 00010 00100 01000 10000 @W:CL159 : gdp_decoder.vhd(52) | Input hsync_i is unused @W:CL159 : gdp_decoder.vhd(61) | Input Rd_i is unused @N:CL201 : gdp_bresenham.vhd(133) | Trying to extract state machine for register state Extracted state machine for register state State machine has 5 reachable states with original encodings of: 00001 00010 00100 01000 10000 @N:CL201 : gdp_character.vhd(198) | Trying to extract state machine for register state Extracted state machine for register state State machine has 4 reachable states with original encodings of: 00 01 10 11 @W:CL159 : gdp_character.vhd(67) | Input rom_data_i is unused @W:CL159 : gdp_character.vhd(69) | Input rom_busy_i is unused @N:CL201 : gdp_kernel.vhd(610) | Trying to extract state machine for register state Extracted state machine for register state State machine has 5 reachable states with original encodings of: 00001 00010 00100 01000 10000 @W:CL159 : gdp_kernel.vhd(54) | Input kernel_ack_i is unused @N:CL201 : gdp_vram.vhd(197) | Trying to extract state machine for register state Extracted state machine for register state State machine has 3 reachable states with original encodings of: 00 01 10 @W:CL159 : gdp_vram.vhd(38) | Input chr_rom_addr_i is unused @W:CL159 : gdp_vram.vhd(40) | Input chr_rom_ena_i is unused @W:CL157 : gdp_top.vhd(329) | Output monitoring_o has undriven bits -- simulation mismatch possible. @N:CL201 : PS2_Decoder.vhd(538) | Trying to extract state machine for register fetch_state Extracted state machine for register fetch_state State machine has 4 reachable states with original encodings of: 00 01 10 11 @N:CL201 : PS2Keyboard.vhd(563) | Trying to extract state machine for register kbd_init_state Extracted state machine for register kbd_init_state State machine has 3 reachable states with original encodings of: 00 01 10 @W:CL246 : PS2Keyboard.vhd(48) | Input port bits 7 to 2 of datain_i(7 downto 0) are unused @N:CL201 : PS2_Interface.vhd(167) | Trying to extract state machine for register state Extracted state machine for register state State machine has 5 reachable states with original encodings of: 00001 00010 00100 01000 10000 @N:CL201 : PS2Mouse.vhd(287) | Trying to extract state machine for register mouse_state Extracted state machine for register mouse_state State machine has 4 reachable states with original encodings of: 00 01 10 11 @W:CL159 : PS2Mouse.vhd(45) | Input DataIn_i is unused @W:CL159 : PS2Mouse.vhd(46) | Input Rd_i is unused @N:CL201 : Ser1.vhd(572) | Trying to extract state machine for register rx_state Extracted state machine for register rx_state State machine has 4 reachable states with original encodings of: 00 01 10 11 @N:CL201 : Ser1.vhd(425) | Trying to extract state machine for register tx_state Extracted state machine for register tx_state State machine has 3 reachable states with original encodings of: 00 01 10 @W:CL159 : gdp_lattice_top.vhd(54) | Input gdphs_wbs_cycle is unused @W:CL159 : gdp_lattice_top.vhd(70) | Input gdphs_wbm_ack is unused @N:CL201 : gide.vhd(127) | Trying to extract state machine for register state Extracted state machine for register state State machine has 25 reachable states with original encodings of: 000000000000000000000000000000000001 000000000000000000000000000000000010 000000000000000000000000000000000100 000000000000000000000000000000001000 000000000000000000000000000000010000 000000000000000000000000000000100000 000000000000000000000000000001000000 000000000000000000000000000010000000 000000000000000000000000100000000000 000000000000000000000001000000000000 000000000000000000000010000000000000 000000000000000000000100000000000000 000000000000000000001000000000000000 000000000000000000010000000000000000 000000000000000000100000000000000000 000000000000001000000000000000000000 000000000000010000000000000000000000 000000000000100000000000000000000000 000000000001000000000000000000000000 000000000100000000000000000000000000 000000010000000000000000000000000000 000000100000000000000000000000000000 000001000000000000000000000000000000 010000000000000000000000000000000000 100000000000000000000000000000000000 @W:CL159 : gide.vhd(39) | Input gide_wbs_cycle is unused @W:CL159 : gide.vhd(48) | Input IDE_INT is unused @W:CL159 : sram.vhd(22) | Input sram_reset_n is unused @W:CL159 : sram.vhd(23) | Input sram_clk is unused @W:CL159 : sram.vhd(31) | Input sram_wbs_cycle is unused @END Process took 0h:00m:05s realtime, 0h:00m:05s cputime # Fri Oct 10 21:51:26 2014 ###########################################################]