Synthesis Report #Build: Synplify Pro F-2012.03L-1 , Build 063R, May 17 2012 #install: C:\Program Files\Lattice\Diamond2.0\diamond\2.0\synpbase #OS: Windows 7 6.1 #Hostname: TORSTEN-PC #Implementation: GDPFPGAII $ Start of Compile #Tue Feb 24 14:41:23 2015 Synopsys VHDL Compiler, version comp201203rcp1, Build 061R, built May 17 2012 @N|Running in 64-bit mode Copyright (C) 1994-2012 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc. @N: CD720 :"C:\Program Files\Lattice\Diamond2.0\diamond\2.0\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns @N:"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gdp_fpgaii_top.vhd":26:7:26:20|Top entity is set to gdp_fpgaii_top. VHDL syntax check successful! File C:\Program Files\Lattice\Diamond2.0\diamond\2.0\cae_library\synthesis\vhdl\xp2.vhd changed - recompiling File D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\nkc16_wb_wrapper.vhd changed - recompiling File D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\FPGA_specific\ps2_fifo.vhd changed - recompiling @N: CD630 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gdp_fpgaii_top.vhd":26:7:26:20|Synthesizing work.gdp_fpgaii_top.rtl @N: CD367 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gdp_fpgaii_top.vhd":636:2:636:6|Instance GDPHS, Port monitoring_o, Bit <3> connection not specified @N: CD367 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gdp_fpgaii_top.vhd":636:2:636:6|Instance GDPHS, Port monitoring_o, Bit <4> connection not specified @N: CD367 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gdp_fpgaii_top.vhd":636:2:636:6|Instance GDPHS, Port monitoring_o, Bit <5> connection not specified @N: CD367 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gdp_fpgaii_top.vhd":636:2:636:6|Instance GDPHS, Port monitoring_o, Bit <6> connection not specified @N: CD367 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gdp_fpgaii_top.vhd":636:2:636:6|Instance GDPHS, Port monitoring_o, Bit <7> connection not specified @N: CD367 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gdp_fpgaii_top.vhd":636:2:636:6|Instance GDPHS, Port monitoring_o, Bit <8> connection not specified @N: CD367 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gdp_fpgaii_top.vhd":636:2:636:6|Instance GDPHS, Port monitoring_o, Bit <9> connection not specified @N: CD367 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gdp_fpgaii_top.vhd":636:2:636:6|Instance GDPHS, Port monitoring_o, Bit <10> connection not specified @N: CD367 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gdp_fpgaii_top.vhd":636:2:636:6|Instance GDPHS, Port monitoring_o, Bit <11> connection not specified @N: CD367 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gdp_fpgaii_top.vhd":636:2:636:6|Instance GDPHS, Port monitoring_o, Bit <12> connection not specified @N: CD367 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gdp_fpgaii_top.vhd":636:2:636:6|Instance GDPHS, Port monitoring_o, Bit <13> connection not specified @N: CD367 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gdp_fpgaii_top.vhd":636:2:636:6|Instance GDPHS, Port monitoring_o, Bit <14> connection not specified @N: CD367 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gdp_fpgaii_top.vhd":636:2:636:6|Instance GDPHS, Port monitoring_o, Bit <15> connection not specified @W: CD638 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gdp_fpgaii_top.vhd":504:8:504:16|Signal debug_sig is undriven @N: CD630 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\sram.vhd":17:7:17:10|Synthesizing work.sram.sram_1 Post processing for work.sram.sram_1 @W: CL169 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\sram.vhd":64:2:64:3|Pruning register ws_cnt(20 downto 0) @N: CD630 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gide.vhd":27:7:27:10|Synthesizing work.gide.behavioral @N: CD231 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gide.vhd":76:16:76:17|Using onehot encoding for type state_type (init="100000000000000000000000000000000000") Post processing for work.gide.behavioral @W: CL271 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gide.vhd":95:4:95:5|Pruning bits 4 to 2 of q(4 downto 0) -- not in use ... @A: CL282 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gide.vhd":128:2:128:3|Feedback mux created for signal gide_wbs_ack -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @N: CD630 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_lattice_top.vhd":28:7:28:21|Synthesizing work.gdp_lattice_top.rtl @W: CD638 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_lattice_top.vhd":438:9:438:14|Signal busyrx is undriven @W: CD638 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_lattice_top.vhd":439:9:439:17|Signal doutparrx is undriven @W: CD638 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_lattice_top.vhd":440:9:440:19|Signal datavalidrx is undriven @W: CD638 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_lattice_top.vhd":441:9:441:22|Signal olddatavalidrx is undriven @W: CD638 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_lattice_top.vhd":457:9:457:15|Signal vdip_cs is undriven @W: CD638 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_lattice_top.vhd":458:9:458:17|Signal vdip_data is undriven @W: CD638 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_lattice_top.vhd":467:9:467:9|Signal q is undriven @N: CD630 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\Timer\Timer.vhd":21:7:21:11|Synthesizing work.timer.rtl Post processing for work.timer.rtl @W: CL271 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\Timer\Timer.vhd":77:6:77:7|Pruning bits 5 to 3 of ctrl_reg(7 downto 0) -- not in use ... @N: CD630 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\SPI\SPI_Interface.vhd":21:7:21:19|Synthesizing work.spi_interface.rtl Post processing for work.spi_interface.rtl @W: CL265 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\SPI\SPI_Interface.vhd":94:6:94:7|Pruning bit 4 of ctrl_reg(7 downto 0) -- not in use ... @N: CD630 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\sound\wf2149ip_top_soc.vhd":20:7:20:22|Synthesizing work.wf2149ip_top_soc.structure @N: CD233 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\sound\wf2149ip_pkg.vhd":20:17:20:18|Using sequential encoding for type buscycles_t @N: CD630 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\sound\wf2149ip_wave.vhd":21:7:21:19|Synthesizing work.wf2149ip_wave.behavior @N: CD233 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\sound\wf2149ip_pkg.vhd":20:17:20:18|Using sequential encoding for type buscycles_t @N: CD630 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\sound\dac.vhd":28:7:28:9|Synthesizing work.dac.rtl Post processing for work.dac.rtl Post processing for work.wf2149ip_wave.behavior @A: CL282 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\sound\wf2149ip_wave.vhd":76:8:76:9|Feedback mux created for signal ENV_RESET -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. Post processing for work.wf2149ip_top_soc.structure @A: CL282 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\sound\wf2149ip_top_soc.vhd":67:8:67:9|Feedback mux created for signal WAV_STRB -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @N: CD630 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\Ser\Ser1.vhd":22:7:22:10|Synthesizing work.ser1.rtl @N: CD233 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\Ser\Ser1.vhd":72:18:72:19|Using sequential encoding for type tx_state_t @N: CD233 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\Ser\Ser1.vhd":105:18:105:19|Using sequential encoding for type rx_state_t @W: CD604 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\Ser\Ser1.vhd":413:6:413:19|OTHERS clause is not synthesized @W: CD604 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\Ser\Ser1.vhd":561:6:561:19|OTHERS clause is not synthesized @N: CD630 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\InputSync-e.vhd":15:7:15:15|Synthesizing work.inputsync.rtl Post processing for work.inputsync.rtl @N: CD630 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\InputSync-e.vhd":15:7:15:15|Synthesizing work.inputsync.rtl Post processing for work.inputsync.rtl Post processing for work.ser1.rtl @W: CL190 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\Ser\Ser1.vhd":195:6:195:7|Optimizing register bit Status_reg(5) to a constant 0 @W: CL190 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\Ser\Ser1.vhd":195:6:195:7|Optimizing register bit Status_reg(7) to a constant 0 @W: CL260 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\Ser\Ser1.vhd":195:6:195:7|Pruning register bit 7 of Status_reg(7 downto 0) @W: CL260 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\Ser\Ser1.vhd":195:6:195:7|Pruning register bit 5 of Status_reg(7 downto 0) @N: CD630 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\PS2_Stuff\PS2Mouse.vhd":28:7:28:14|Synthesizing work.ps2mouse.rtl @N: CD233 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\PS2_Stuff\PS2Mouse.vhd":88:22:88:23|Using sequential encoding for type mouse_state_t @N: CD233 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\PS2_Stuff\PS2Mouse.vhd":89:27:89:28|Using sequential encoding for type mouse_send_state_t @W: CD604 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\PS2_Stuff\PS2Mouse.vhd":241:10:241:23|OTHERS clause is not synthesized @W: CD604 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\PS2_Stuff\PS2Mouse.vhd":277:10:277:23|OTHERS clause is not synthesized @W: CD604 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\PS2_Stuff\PS2Mouse.vhd":280:6:280:19|OTHERS clause is not synthesized @N: CD630 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\PS2_Stuff\PS2_Interface.vhd":28:7:28:19|Synthesizing work.ps2_interface.rtl @N: CD233 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\PS2_Stuff\PS2_Interface.vhd":67:24:67:25|Using sequential encoding for type ps2direction_t @N: CD231 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\PS2_Stuff\PS2_Interface.vhd":68:24:68:25|Using onehot encoding for type state_t (idle="10000") @N: CD233 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\PS2_Stuff\PS2_Interface.vhd":69:24:69:25|Using sequential encoding for type clkedge_t Post processing for work.ps2_interface.rtl Post processing for work.ps2mouse.rtl @W: CL279 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\PS2_Stuff\PS2Mouse.vhd":287:4:287:5|Pruning register bits 7 to 6 of button_stat(7 downto 0) @N: CD630 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\PS2_Stuff\PS2Keyboard.vhd":28:7:28:17|Synthesizing work.ps2keyboard.rtl @N: CD233 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\PS2_Stuff\PS2Keyboard.vhd":118:24:118:25|Using sequential encoding for type fifordstate_t @N: CD233 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\PS2_Stuff\PS2Keyboard.vhd":120:25:120:26|Using sequential encoding for type kbd_init_state_t @N: CD233 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\PS2_Stuff\PS2Keyboard.vhd":121:25:121:26|Using sequential encoding for type kbd_send_state_t @W: CD604 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\PS2_Stuff\PS2Keyboard.vhd":435:10:435:23|OTHERS clause is not synthesized @W: CD604 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\PS2_Stuff\PS2Keyboard.vhd":438:6:438:19|OTHERS clause is not synthesized @W: CD604 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\PS2_Stuff\PS2Keyboard.vhd":527:10:527:23|OTHERS clause is not synthesized @W: CD604 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\PS2_Stuff\PS2Keyboard.vhd":553:10:553:23|OTHERS clause is not synthesized @W: CD604 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\PS2_Stuff\PS2Keyboard.vhd":556:6:556:19|OTHERS clause is not synthesized @N: CD630 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\FPGA_specific\ps2_fifo.vhd":15:7:15:14|Synthesizing work.ps2_fifo.structure @N: CD630 :"C:\Program Files\Lattice\Diamond2.0\diamond\2.0\cae_library\synthesis\vhdl\xp.vhd":1549:10:1549:16|Synthesizing work.rom16x1.syn_black_box Post processing for work.rom16x1.syn_black_box @N: CD630 :"C:\Program Files\Lattice\Diamond2.0\diamond\2.0\cae_library\synthesis\vhdl\xp.vhd":542:10:542:16|Synthesizing work.fd1p3dx.syn_black_box Post processing for work.fd1p3dx.syn_black_box @N: CD630 :"C:\Program Files\Lattice\Diamond2.0\diamond\2.0\cae_library\synthesis\vhdl\xp.vhd":662:10:662:16|Synthesizing work.fd1s3bx.syn_black_box Post processing for work.fd1s3bx.syn_black_box @N: CD630 :"C:\Program Files\Lattice\Diamond2.0\diamond\2.0\cae_library\synthesis\vhdl\xp.vhd":673:10:673:16|Synthesizing work.fd1s3dx.syn_black_box Post processing for work.fd1s3dx.syn_black_box @N: CD630 :"C:\Program Files\Lattice\Diamond2.0\diamond\2.0\cae_library\synthesis\vhdl\xp.vhd":384:10:384:17|Synthesizing work.dpr16x2b.syn_black_box Post processing for work.dpr16x2b.syn_black_box @N: CD630 :"C:\Program Files\Lattice\Diamond2.0\diamond\2.0\cae_library\synthesis\vhdl\xp.vhd":1643:10:1643:12|Synthesizing work.vlo.syn_black_box Post processing for work.vlo.syn_black_box @N: CD630 :"C:\Program Files\Lattice\Diamond2.0\diamond\2.0\cae_library\synthesis\vhdl\xp.vhd":346:10:346:12|Synthesizing work.cu2.syn_black_box Post processing for work.cu2.syn_black_box @N: CD630 :"C:\Program Files\Lattice\Diamond2.0\diamond\2.0\cae_library\synthesis\vhdl\xp.vhd":1635:10:1635:12|Synthesizing work.vhi.syn_black_box Post processing for work.vhi.syn_black_box @N: CD630 :"C:\Program Files\Lattice\Diamond2.0\diamond\2.0\cae_library\synthesis\vhdl\xp.vhd":212:10:212:14|Synthesizing work.ageb2.syn_black_box Post processing for work.ageb2.syn_black_box @N: CD630 :"C:\Program Files\Lattice\Diamond2.0\diamond\2.0\cae_library\synthesis\vhdl\xp.vhd":471:10:471:14|Synthesizing work.fadd2.syn_black_box Post processing for work.fadd2.syn_black_box @N: CD630 :"C:\Program Files\Lattice\Diamond2.0\diamond\2.0\cae_library\synthesis\vhdl\xp.vhd":224:10:224:14|Synthesizing work.aleb2.syn_black_box Post processing for work.aleb2.syn_black_box @N: CD630 :"C:\Program Files\Lattice\Diamond2.0\diamond\2.0\cae_library\synthesis\vhdl\xp.vhd":186:10:186:12|Synthesizing work.cb2.syn_black_box Post processing for work.cb2.syn_black_box @N: CD630 :"C:\Program Files\Lattice\Diamond2.0\diamond\2.0\cae_library\synthesis\vhdl\xp.vhd":236:10:236:13|Synthesizing work.and2.syn_black_box Post processing for work.and2.syn_black_box @N: CD630 :"C:\Program Files\Lattice\Diamond2.0\diamond\2.0\cae_library\synthesis\vhdl\xp.vhd":989:10:989:12|Synthesizing work.inv.syn_black_box Post processing for work.inv.syn_black_box @N: CD630 :"C:\Program Files\Lattice\Diamond2.0\diamond\2.0\cae_library\synthesis\vhdl\xp.vhd":1711:10:1711:13|Synthesizing work.xor2.syn_black_box Post processing for work.xor2.syn_black_box Post processing for work.ps2_fifo.structure @W: CL168 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\FPGA_specific\ps2_fifo.vhd":316:4:316:10|Pruning instance r_ctr_1 -- not in use ... @W: CL168 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\FPGA_specific\ps2_fifo.vhd":305:4:305:10|Pruning instance w_ctr_1 -- not in use ... @W: CL168 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\FPGA_specific\ps2_fifo.vhd":236:4:236:7|Pruning instance FF_7 -- not in use ... @W: CL168 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\FPGA_specific\ps2_fifo.vhd":224:4:224:8|Pruning instance FF_10 -- not in use ... @N: CD630 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\PS2_Stuff\PS2_Decoder.vhd":20:7:20:17|Synthesizing work.ps2_decoder.rtl @N: CD233 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\PS2_Stuff\PS2_Decoder.vhd":42:21:42:22|Using sequential encoding for type fetch_state_t @W: CD604 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\PS2_Stuff\PS2_Decoder.vhd":528:8:528:21|OTHERS clause is not synthesized Post processing for work.ps2_decoder.rtl @W: CL190 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\PS2_Stuff\PS2_Decoder.vhd":538:4:538:5|Optimizing register bit KeyStates(1) to a constant 0 @W: CL260 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\PS2_Stuff\PS2_Decoder.vhd":538:4:538:5|Pruning register bit 1 of KeyStates(7 downto 0) Post processing for work.ps2keyboard.rtl @A: CL282 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\PS2_Stuff\PS2Keyboard.vhd":446:4:446:5|Feedback mux created for signal DataOut_o[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @W: CL111 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\PS2_Stuff\PS2Keyboard.vhd":446:4:446:5|All reachable assignments to KeyOptsReg(2) assign '0'; register removed by optimization @W: CL111 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\PS2_Stuff\PS2Keyboard.vhd":446:4:446:5|All reachable assignments to KeyOptsReg(3) assign '0'; register removed by optimization @W: CL111 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\PS2_Stuff\PS2Keyboard.vhd":446:4:446:5|All reachable assignments to KeyOptsReg(4) assign '0'; register removed by optimization @W: CL111 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\PS2_Stuff\PS2Keyboard.vhd":446:4:446:5|All reachable assignments to KeyOptsReg(5) assign '0'; register removed by optimization @W: CL111 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\PS2_Stuff\PS2Keyboard.vhd":446:4:446:5|All reachable assignments to KeyOptsReg(6) assign '0'; register removed by optimization @N: CD630 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_top.vhd":25:7:25:13|Synthesizing work.gdp_top.rtl @W: CD326 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_top.vhd":362:2:362:5|Port rom_ena_o of entity work.gdp_vram is unconnected @W: CD796 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_top.vhd":207:9:207:17|Bit 8 of signal dataout_s is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. @W: CD796 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_top.vhd":207:9:207:17|Bit 9 of signal dataout_s is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. @W: CD796 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_top.vhd":207:9:207:17|Bit 10 of signal dataout_s is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. @W: CD796 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_top.vhd":207:9:207:17|Bit 11 of signal dataout_s is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. @W: CD796 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_top.vhd":207:9:207:17|Bit 12 of signal dataout_s is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. @W: CD796 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_top.vhd":207:9:207:17|Bit 13 of signal dataout_s is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. @W: CD796 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_top.vhd":207:9:207:17|Bit 14 of signal dataout_s is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. @W: CD796 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_top.vhd":207:9:207:17|Bit 15 of signal dataout_s is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. @W: CD638 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_top.vhd":208:9:208:18|Signal monitoring is undriven @N: CD630 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":24:7:24:14|Synthesizing work.gdp_vram.rtl @N: CD231 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":82:15:82:16|Using onehot encoding for type state_t (idle_e="10000000") @N: CD233 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":119:16:119:17|Using sequential encoding for type mstate_t @W: CD434 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":131:16:131:26|Signal ram_address in the sensitivity list is not used in the process @W: CD434 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":131:65:131:71|Signal wr_data in the sensitivity list is not used in the process @W: CD434 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":131:73:131:79|Signal rd_data in the sensitivity list is not used in the process @W: CD434 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":131:81:131:88|Signal ram_wren in the sensitivity list is not used in the process @W: CD434 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":132:56:132:66|Signal kernel_data in the sensitivity list is not used in the process @W: CD434 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":132:84:132:97|Signal kernel_wr_data in the sensitivity list is not used in the process @W: CD434 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":133:10:133:20|Signal host_addr_i in the sensitivity list is not used in the process @W: CD434 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":133:22:133:30|Signal host_wr_i in the sensitivity list is not used in the process @W: CD434 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":133:32:133:41|Signal host_req_i in the sensitivity list is not used in the process @W: CD434 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":133:43:133:55|Signal host_req_pend in the sensitivity list is not used in the process @W: CD434 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":133:57:133:65|Signal host_data in the sensitivity list is not used in the process @W: CD434 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":133:67:133:78|Signal host_wr_data in the sensitivity list is not used in the process @W: CD434 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":134:56:134:69|Signal chr_rom_addr_i in the sensitivity list is not used in the process @W: CD434 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":134:72:134:79|Signal rom_data in the sensitivity list is not used in the process @W: CD434 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":134:81:134:87|Signal blank_i in the sensitivity list is not used in the process @W: CG296 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":131:2:131:8|Incomplete sensitivity list - assuming completeness @W: CG290 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":206:5:206:11|Referenced variable ram_sel is not in sensitivity list @W: CD434 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":367:46:367:52|Signal blank_i in the sensitivity list is not used in the process @W: CD604 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":451:3:451:16|OTHERS clause is not synthesized @W: CD434 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":417:21:417:25|Signal clk_i in the sensitivity list is not used in the process @W: CD434 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":417:28:417:36|Signal reset_n_i in the sensitivity list is not used in the process @W: CD434 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":417:46:417:56|Signal next_mstate in the sensitivity list is not used in the process @W: CD434 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":418:74:418:85|Signal kernel_req_i in the sensitivity list is not used in the process @W: CG296 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":417:13:417:19|Incomplete sensitivity list - assuming completeness @W: CG290 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":449:21:449:30|Referenced variable sram_ack_i is not in sensitivity list @W: CD638 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":84:9:84:20|Signal host_wr_data is undriven @W: CD638 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":85:9:85:22|Signal kernel_wr_data is undriven @W: CD638 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":98:9:98:14|Signal ram_en is undriven @W: CD638 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":99:9:99:15|Signal srom_en is undriven @W: CD638 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":101:9:101:21|Signal srom_req_pend is undriven @W: CD638 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":102:9:102:17|Signal srom_data is undriven @W: CD638 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":108:9:108:20|Signal next_wr_data is undriven @W: CD638 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":109:9:109:19|Signal set_wr_data is undriven @W: CD638 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":110:9:110:21|Signal next_host_ack is undriven @W: CD638 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":111:9:111:21|Signal host_req_pend is undriven @W: CD638 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":112:9:112:21|Signal set_host_data is undriven @W: CD638 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":113:9:113:17|Signal host_data is undriven @W: CD638 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":113:19:113:32|Signal next_host_data is undriven @W: CD638 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":116:9:116:15|Signal blank_s is undriven @W: CD638 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":120:17:120:27|Signal next_mstate is undriven Post processing for work.gdp_vram.rtl @W: CL240 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":111:9:111:21|host_req_pend is not assigned a value (floating) -- simulation mismatch possible. @W: CL252 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":85:9:85:22|Bit 0 of signal kernel_wr_data is floating -- simulation mismatch possible. @W: CL252 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":85:9:85:22|Bit 1 of signal kernel_wr_data is floating -- simulation mismatch possible. @W: CL252 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":85:9:85:22|Bit 2 of signal kernel_wr_data is floating -- simulation mismatch possible. @W: CL252 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":85:9:85:22|Bit 3 of signal kernel_wr_data is floating -- simulation mismatch possible. @W: CL252 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":85:9:85:22|Bit 4 of signal kernel_wr_data is floating -- simulation mismatch possible. @W: CL252 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":85:9:85:22|Bit 5 of signal kernel_wr_data is floating -- simulation mismatch possible. @W: CL252 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":85:9:85:22|Bit 6 of signal kernel_wr_data is floating -- simulation mismatch possible. @W: CL252 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":85:9:85:22|Bit 7 of signal kernel_wr_data is floating -- simulation mismatch possible. @W: CL240 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":70:4:70:12|rom_ena_o is not assigned a value (floating) -- simulation mismatch possible. @W: CL240 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":38:4:38:14|host_busy_o is not assigned a value (floating) -- simulation mismatch possible. @A: CL282 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":257:4:257:5|Feedback mux created for signal wr_data[15:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @W: CL117 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":422:2:422:5|Latch generated from process for signal host_data_o(15 downto 0); possible missing assignment in an if or case statement. @W: CL117 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":422:2:422:5|Latch generated from process for signal sram_data_i_tmp(15 downto 0); possible missing assignment in an if or case statement. @W: CL190 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":257:4:257:5|Optimizing register bit ram_address(17) to a constant 0 @W: CL190 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":257:4:257:5|Optimizing register bit ram_address(18) to a constant 0 @W: CL279 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":257:4:257:5|Pruning register bits 18 to 17 of ram_address(18 downto 0) @N: CD630 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_kernel.vhd":22:7:22:16|Synthesizing work.gdp_kernel.rtl @N: CD231 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_kernel.vhd":178:15:178:16|Using onehot encoding for type state_t (idle_e="10000") @N: CD231 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_global-p.vhd":57:17:57:18|Using onehot encoding for type drawcmd_t (idle_e="10000") @W: CD604 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_kernel.vhd":620:6:620:19|OTHERS clause is not synthesized @N: CD630 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_character.vhd":21:7:21:19|Synthesizing work.gdp_character.rtl @N: CD233 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_character.vhd":105:20:105:21|Using sequential encoding for type char_state_t @W: CD604 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_character.vhd":446:8:446:21|OTHERS clause is not synthesized @W: CD434 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_character.vhd":271:40:271:49|Signal rom_busy_i in the sensitivity list is not used in the process @W: CD434 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_character.vhd":271:52:271:58|Signal rom_ena in the sensitivity list is not used in the process @N: CD630 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_font_ram.vhd":8:7:8:18|Synthesizing work.gdp_font_ram.rtl Post processing for work.gdp_font_ram.rtl @N: CL134 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_font_ram.vhd":23:9:23:12|Found RAM iram, depth=1024, width=8 Post processing for work.gdp_character.rtl @W: CL169 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_character.vhd":198:6:198:7|Pruning register finished @W: CL169 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_character.vhd":198:6:198:7|Pruning register rom_ena @N: CD630 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_bresenham.vhd":21:7:21:19|Synthesizing work.gdp_bresenham.rtl @N: CD231 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_bresenham.vhd":72:20:72:21|Using onehot encoding for type bres_state_t (idle_e="10000") Post processing for work.gdp_bresenham.rtl @W: CL190 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_bresenham.vhd":133:6:133:7|Optimizing register bit edec(0) to a constant 0 @W: CL190 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_bresenham.vhd":133:6:133:7|Optimizing register bit einc(0) to a constant 0 @W: CL260 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_bresenham.vhd":133:6:133:7|Pruning register bit 0 of einc(10 downto 0) @W: CL260 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_bresenham.vhd":133:6:133:7|Pruning register bit 0 of edec(10 downto 0) @N: CD630 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_decoder.vhd":22:7:22:17|Synthesizing work.gdp_decoder.rtl @N: CD231 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_global-p.vhd":57:17:57:18|Using onehot encoding for type drawcmd_t (idle_e="10000") Post processing for work.gdp_decoder.rtl Post processing for work.gdp_kernel.rtl @W: CL271 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_kernel.vhd":365:4:365:5|Pruning bits 31 to 25 of q(31 downto 0) -- not in use ... @N: CD630 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_video.vhd":23:7:23:15|Synthesizing work.gdp_video.rtl @N: CD233 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_video.vhd":90:18:90:19|Using sequential encoding for type rd_state_t @W: CD604 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_video.vhd":281:6:281:19|OTHERS clause is not synthesized @W: CD434 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_video.vhd":220:42:220:51|Signal rd_address in the sensitivity list is not used in the process @W: CD434 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_video.vhd":221:23:221:30|Signal rd_ack_i in the sensitivity list is not used in the process @N: CD630 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_clut.vhd":22:7:22:14|Synthesizing work.gdp_clut.rtl Post processing for work.gdp_clut.rtl Post processing for work.gdp_video.rtl @W: CL240 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_video.vhd":62:7:62:18|monitoring_o is not assigned a value (floating) -- simulation mismatch possible. @A: CL282 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_video.vhd":157:4:157:5|Feedback mux created for signal isCursor -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. Post processing for work.gdp_top.rtl @N: CD630 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_bi.vhd":22:7:22:12|Synthesizing work.gdp_bi.rtl @N: CD630 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\InputSync-e.vhd":15:7:15:15|Synthesizing work.inputsync.rtl Post processing for work.inputsync.rtl Post processing for work.gdp_bi.rtl Post processing for work.gdp_lattice_top.rtl @W: CL252 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_lattice_top.vhd":458:9:458:17|Bit 0 of signal vdip_data is floating -- simulation mismatch possible. @W: CL252 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_lattice_top.vhd":458:9:458:17|Bit 1 of signal vdip_data is floating -- simulation mismatch possible. @W: CL252 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_lattice_top.vhd":458:9:458:17|Bit 2 of signal vdip_data is floating -- simulation mismatch possible. @W: CL252 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_lattice_top.vhd":458:9:458:17|Bit 3 of signal vdip_data is floating -- simulation mismatch possible. @W: CL252 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_lattice_top.vhd":458:9:458:17|Bit 4 of signal vdip_data is floating -- simulation mismatch possible. @W: CL252 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_lattice_top.vhd":458:9:458:17|Bit 5 of signal vdip_data is floating -- simulation mismatch possible. @W: CL252 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_lattice_top.vhd":458:9:458:17|Bit 6 of signal vdip_data is floating -- simulation mismatch possible. @W: CL252 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_lattice_top.vhd":458:9:458:17|Bit 7 of signal vdip_data is floating -- simulation mismatch possible. @W: CL240 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_lattice_top.vhd":457:9:457:15|vdip_cs is not assigned a value (floating) -- simulation mismatch possible. @W: CL169 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_lattice_top.vhd":473:1:473:2|Pruning register shreg(9 downto 0) @N: CD630 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gdp_intercon.vhd":18:7:18:21|Synthesizing work.wb_interconnect.intercon @W: CD638 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gdp_intercon.vhd":139:11:139:16|Signal gdp_cs is undriven @W: CD638 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gdp_intercon.vhd":140:8:140:13|Signal sfr_cs is undriven @W: CD638 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gdp_intercon.vhd":141:8:141:13|Signal col_cs is undriven @W: CD638 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gdp_intercon.vhd":142:8:142:14|Signal clut_cs is undriven @W: CD638 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gdp_intercon.vhd":143:8:143:13|Signal key_cs is undriven @W: CD638 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gdp_intercon.vhd":144:8:144:13|Signal dip_cs is undriven @W: CD638 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gdp_intercon.vhd":145:8:145:15|Signal mouse_cs is undriven @W: CD638 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gdp_intercon.vhd":146:8:146:13|Signal ser_cs is undriven @W: CD638 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gdp_intercon.vhd":147:8:147:15|Signal sound_cs is undriven @W: CD638 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gdp_intercon.vhd":148:8:148:13|Signal spi_cs is undriven @W: CD638 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gdp_intercon.vhd":149:8:149:12|Signal t1_cs is undriven @W: CD638 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gdp_intercon.vhd":150:8:150:14|Signal vdip_cs is undriven @W: CD638 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gdp_intercon.vhd":151:8:151:15|Signal kopts_cs is undriven @W: CD638 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gdp_intercon.vhd":154:8:154:19|Signal sram_address is undriven @W: CD638 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gdp_intercon.vhd":155:8:155:20|Signal sram_readdata is undriven @W: CD638 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gdp_intercon.vhd":156:8:156:18|Signal sram_buffer is undriven @W: CD638 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gdp_intercon.vhd":157:8:157:21|Signal sram_writedata is undriven @W: CD638 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gdp_intercon.vhd":158:11:158:18|Signal sram_ack is undriven @W: CD638 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gdp_intercon.vhd":159:11:159:21|Signal sram_strobe is undriven @W: CD638 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gdp_intercon.vhd":160:11:160:20|Signal sram_cycle is undriven @W: CD638 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gdp_intercon.vhd":161:11:161:20|Signal sram_write is undriven @W: CD638 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gdp_intercon.vhd":162:11:162:18|Signal sram_sel is undriven @W: CD638 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gdp_intercon.vhd":164:8:164:22|Signal grant_host_sram is undriven @W: CD638 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gdp_intercon.vhd":165:8:165:23|Signal grant_gdphs_sram is undriven @W: CD638 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gdp_intercon.vhd":167:8:167:20|Signal host_sram_ack is undriven Post processing for work.wb_interconnect.intercon @W: CL240 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gdp_intercon.vhd":110:2:110:8|debug_o is not assigned a value (floating) -- simulation mismatch possible. @W: CL240 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gdp_intercon.vhd":31:5:31:10|IRQ1_o is not assigned a value (floating) -- simulation mismatch possible. @W: CL240 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gdp_intercon.vhd":30:5:30:10|IRQ0_o is not assigned a value (floating) -- simulation mismatch possible. @W: CL240 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gdp_intercon.vhd":29:2:29:7|nNMI_o is not assigned a value (floating) -- simulation mismatch possible. @N: CD630 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\nkc16_wb_wrapper.vhd":26:7:26:22|Synthesizing work.nkc16_wb_wrapper.rtl @W: CD434 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\nkc16_wb_wrapper.vhd":213:14:213:24|Signal wrapper_clk in the sensitivity list is not used in the process @W: CD434 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\nkc16_wb_wrapper.vhd":306:36:306:41|Signal strobe in the sensitivity list is not used in the process @W: CG296 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\nkc16_wb_wrapper.vhd":306:1:306:7|Incomplete sensitivity list - assuming completeness @W: CG290 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\nkc16_wb_wrapper.vhd":313:11:313:17|Referenced variable fpga_en is not in sensitivity list Post processing for work.nkc16_wb_wrapper.rtl @W: CL240 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\nkc16_wb_wrapper.vhd":64:1:64:7|debug_o is not assigned a value (floating) -- simulation mismatch possible. Post processing for work.gdp_fpgaii_top.rtl @W: CL246 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gdp_intercon.vhd":108:2:108:18|Input port bits 13 to 0 of wrapper_cs_vector(16 downto 0) are unused @W: CL159 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gdp_intercon.vhd":64:2:64:8|Input Hsync_i is unused @W: CL159 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gdp_intercon.vhd":65:8:65:14|Input Vsync_i is unused @N: CL201 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_video.vhd":291:4:291:5|Trying to extract state machine for register rd_state Extracted state machine for register rd_state State machine has 4 reachable states with original encodings of: 00 01 10 11 @W: CL247 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_video.vhd":54:4:54:8|Input port bit 11 of cx1_i(11 downto 0) is unused @W: CL247 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_video.vhd":55:4:55:8|Input port bit 11 of cx2_i(11 downto 0) is unused @W: CL247 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_video.vhd":56:4:56:8|Input port bit 11 of cy1_i(11 downto 0) is unused @W: CL247 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_video.vhd":57:4:57:8|Input port bit 11 of cy2_i(11 downto 0) is unused @W: CL159 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_video.vhd":33:7:33:14|Input rd_ack_i is unused @N: CL201 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_decoder.vhd":188:4:188:5|Trying to extract state machine for register drawCmd Extracted state machine for register drawCmd State machine has 5 reachable states with original encodings of: 00001 00010 00100 01000 10000 @W: CL159 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_decoder.vhd":52:7:52:13|Input hsync_i is unused @W: CL159 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_decoder.vhd":61:7:61:10|Input Rd_i is unused @N: CL201 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_bresenham.vhd":133:6:133:7|Trying to extract state machine for register state Extracted state machine for register state State machine has 5 reachable states with original encodings of: 00001 00010 00100 01000 10000 @N: CL201 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_character.vhd":198:6:198:7|Trying to extract state machine for register state Extracted state machine for register state State machine has 4 reachable states with original encodings of: 00 01 10 11 @W: CL159 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_character.vhd":67:7:67:16|Input rom_data_i is unused @W: CL159 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_character.vhd":69:7:69:16|Input rom_busy_i is unused @N: CL201 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_kernel.vhd":627:4:627:5|Trying to extract state machine for register state Extracted state machine for register state State machine has 5 reachable states with original encodings of: 00001 00010 00100 01000 10000 @W: CL159 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_kernel.vhd":54:7:54:18|Input kernel_ack_i is unused @N: CL201 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":369:1:369:2|Trying to extract state machine for register mstate Extracted state machine for register mstate State machine has 3 reachable states with original encodings of: 00 01 10 @N: CL201 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":257:4:257:5|Trying to extract state machine for register state Extracted state machine for register state State machine has 3 reachable states with original encodings of: 00000001 00000010 00001000 @W: CL159 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":50:4:50:17|Input chr_rom_addr_i is unused @W: CL159 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_vram.vhd":52:4:52:16|Input chr_rom_ena_i is unused @W: CL247 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_top.vhd":33:7:33:11|Input port bit 19 of adr_i(19 downto 0) is unused @N: CL201 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\PS2_Stuff\PS2_Decoder.vhd":538:4:538:5|Trying to extract state machine for register fetch_state Extracted state machine for register fetch_state State machine has 4 reachable states with original encodings of: 00 01 10 11 @N: CL201 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\PS2_Stuff\PS2Keyboard.vhd":563:4:563:5|Trying to extract state machine for register kbd_init_state Extracted state machine for register kbd_init_state State machine has 3 reachable states with original encodings of: 00 01 10 @W: CL246 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\PS2_Stuff\PS2Keyboard.vhd":48:4:48:11|Input port bits 7 to 2 of datain_i(7 downto 0) are unused @N: CL201 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\PS2_Stuff\PS2_Interface.vhd":167:4:167:5|Trying to extract state machine for register state Extracted state machine for register state State machine has 5 reachable states with original encodings of: 00001 00010 00100 01000 10000 @N: CL201 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\PS2_Stuff\PS2Mouse.vhd":287:4:287:5|Trying to extract state machine for register mouse_state Extracted state machine for register mouse_state State machine has 4 reachable states with original encodings of: 00 01 10 11 @W: CL159 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\PS2_Stuff\PS2Mouse.vhd":45:4:45:11|Input DataIn_i is unused @W: CL159 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\PS2_Stuff\PS2Mouse.vhd":46:4:46:7|Input Rd_i is unused @N: CL201 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\Ser\Ser1.vhd":571:6:571:7|Trying to extract state machine for register rx_state Extracted state machine for register rx_state State machine has 4 reachable states with original encodings of: 00 01 10 11 @N: CL201 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\Ser\Ser1.vhd":424:6:424:7|Trying to extract state machine for register tx_state Extracted state machine for register tx_state State machine has 3 reachable states with original encodings of: 00 01 10 @W: CL246 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_lattice_top.vhd":39:2:39:16|Input port bits 15 to 14 of gdphs_cs_vector(16 downto 0) are unused @W: CL247 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\GDP64HSFPGA\rtl\gdp_lattice_top.vhd":39:2:39:16|Input port bit 1 of gdphs_cs_vector(16 downto 0) is unused @N: CL201 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gide.vhd":128:2:128:3|Trying to extract state machine for register state Extracted state machine for register state State machine has 25 reachable states with original encodings of: 000000000000000000000000000000000001 000000000000000000000000000000000010 000000000000000000000000000000000100 000000000000000000000000000000001000 000000000000000000000000000000010000 000000000000000000000000000000100000 000000000000000000000000000001000000 000000000000000000000000000010000000 000000000000000000000000100000000000 000000000000000000000001000000000000 000000000000000000000010000000000000 000000000000000000000100000000000000 000000000000000000001000000000000000 000000000000000000010000000000000000 000000000000000000100000000000000000 000000000000001000000000000000000000 000000000000010000000000000000000000 000000000000100000000000000000000000 000000000001000000000000000000000000 000000000100000000000000000000000000 000000010000000000000000000000000000 000000100000000000000000000000000000 000001000000000000000000000000000000 010000000000000000000000000000000000 100000000000000000000000000000000000 @W: CL159 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gide.vhd":40:3:40:16|Input gide_wbs_cycle is unused @W: CL159 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\gide.vhd":49:12:49:18|Input IDE_INT is unused @W: CL159 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\sram.vhd":22:2:22:13|Input sram_reset_n is unused @W: CL159 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\sram.vhd":23:2:23:9|Input sram_clk is unused @W: CL159 :"D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\vhdl\sram.vhd":31:8:31:21|Input sram_wbs_cycle is unused @END Process took 0h:00m:03s realtime, 0h:00m:03s cputime # Tue Feb 24 14:41:26 2015 ###########################################################] Premap Report Synopsys Lattice Technology Pre-mapping, Version maplat, Build 437R, Built Jul 16 2012 10:38:54 Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc. Product Version F-2012.03L-1 Mapper Startup Complete (Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB) @L: D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\GDPFPGAII_GDPFPGAII_scck.rpt Printing clock summary report in "D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\GDPFPGAII_GDPFPGAII_scck.rpt" file @N: MF248 |Running in 64-bit mode. @N: MF257 |Gated clock conversion enabled @N: MF546 |Generated clock conversion enabled Design Input Complete (Time elapsed 0h:00m:00s; Memory used current: 97MB peak: 98MB) Mapper Initialization Complete (Time elapsed 0h:00m:00s; Memory used current: 97MB peak: 98MB) Start loading timing files (Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 111MB) Finished loading timing files (Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB) @W: BN287 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_clut.vhd":56:3:56:4|Register clut_15[8:0] with reset has an initial value of 1. Ignoring initial value. @W: BN287 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_clut.vhd":56:3:56:4|Register clut_14[8:0] with reset has an initial value of 1. Ignoring initial value. @W: BN287 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_clut.vhd":56:3:56:4|Register clut_13[8:0] with reset has an initial value of 1. Ignoring initial value. @W: BN287 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_clut.vhd":56:3:56:4|Register clut_12[8:0] with reset has an initial value of 1. Ignoring initial value. @W: BN287 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_clut.vhd":56:3:56:4|Register clut_11[8:0] with reset has an initial value of 1. Ignoring initial value. @W: BN287 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_clut.vhd":56:3:56:4|Register clut_10[8:0] with reset has an initial value of 1. Ignoring initial value. @W: BN287 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_clut.vhd":56:3:56:4|Register clut_9[8:0] with reset has an initial value of 1. Ignoring initial value. @W: BN287 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_clut.vhd":56:3:56:4|Register clut_8[8:0] with reset has an initial value of 1. Ignoring initial value. @W: BN287 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_clut.vhd":56:3:56:4|Register clut_7[8:0] with reset has an initial value of 1. Ignoring initial value. @W: BN287 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_clut.vhd":56:3:56:4|Register clut_6[8:0] with reset has an initial value of 1. Ignoring initial value. @W: BN287 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_clut.vhd":56:3:56:4|Register clut_5[8:0] with reset has an initial value of 1. Ignoring initial value. @W: BN287 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_clut.vhd":56:3:56:4|Register clut_4[8:0] with reset has an initial value of 1. Ignoring initial value. @W: BN287 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_clut.vhd":56:3:56:4|Register clut_3[8:0] with reset has an initial value of 1. Ignoring initial value. @W: BN287 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_clut.vhd":56:3:56:4|Register clut_2[8:0] with reset has an initial value of 1. Ignoring initial value. @W: FX474 |User-specified initial value found in some of the sequential elements. Applying an initial value to a register may not produce optimum synthesis results. For example, registers with initial values may become preserved which would prevent retiming/pipelining from being performed. To improve synthesis results, remove register initialization from the RTL code. Clock Summary ************** Start Requested Requested Clock Clock Clock Frequency Period Type Group ---------------------------------------------------------------------------------------------------------------------------- System 1.0 MHz 1000.000 system system_clkgroup gdp_fpgaii_top|clk_i 200.0 MHz 5.000 inferred Inferred_clkgroup_0 gide|q_derived_clock[1] 200.0 MHz 5.000 derived (from gdp_fpgaii_top|clk_i) Inferred_clkgroup_0 gdp_vram|mstate_derived_clock[2] 200.0 MHz 5.000 derived (from gdp_fpgaii_top|clk_i) Inferred_clkgroup_0 ============================================================================================================================ @W: MT529 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\nkc16_wb_wrapper.vhd":185:6:185:7|Found inferred clock gdp_fpgaii_top|clk_i which controls 1370 sequential elements including NKCIF/write. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. syn_allowed_resources : blockrams=10 set on top level netlist gdp_fpgaii_top Finished Pre Mapping Phase. (Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 138MB) Pre-mapping successful! At Mapper Exit (Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 138MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Tue Feb 24 14:41:29 2015 ###########################################################] Map & Optimize Report Synopsys Lattice Technology Mapper, Version maplat, Build 437R, Built Jul 16 2012 10:38:54 Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc. Product Version F-2012.03L-1 Mapper Startup Complete (Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB) @N: MF248 |Running in 64-bit mode. @N: MF257 |Gated clock conversion enabled @N: MF546 |Generated clock conversion enabled Design Input Complete (Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB) Mapper Initialization Complete (Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB) Start loading timing files (Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 105MB) Finished loading timing files (Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 107MB) @N: MF203 |Set autoconstraint_io Starting Optimization and Mapping (Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 137MB) @W: MO111 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_vram.vhd":74:4:74:15|Tristate driver monitoring_o_1 on net monitoring_o_1 has its enable tied to GND (module gdp_vram) @W: MO111 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_vram.vhd":74:4:74:15|Tristate driver monitoring_o_2 on net monitoring_o_2 has its enable tied to GND (module gdp_vram) @W: MO111 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_vram.vhd":74:4:74:15|Tristate driver monitoring_o_3 on net monitoring_o_3 has its enable tied to GND (module gdp_vram) @W: MO111 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_vram.vhd":74:4:74:15|Tristate driver monitoring_o_4 on net monitoring_o_4 has its enable tied to GND (module gdp_vram) @W: MO111 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_vram.vhd":74:4:74:15|Tristate driver monitoring_o_5 on net monitoring_o_5 has its enable tied to GND (module gdp_vram) @W: MO111 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_vram.vhd":74:4:74:15|Tristate driver monitoring_o_6 on net monitoring_o_6 has its enable tied to GND (module gdp_vram) @W: MO111 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_vram.vhd":74:4:74:15|Tristate driver monitoring_o_7 on net monitoring_o_7 has its enable tied to GND (module gdp_vram) @W: MO111 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_vram.vhd":74:4:74:15|Tristate driver monitoring_o_8 on net monitoring_o_8 has its enable tied to GND (module gdp_vram) @W: MO111 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_vram.vhd":74:4:74:15|Tristate driver monitoring_o_9 on net monitoring_o_9 has its enable tied to GND (module gdp_vram) @W: MO111 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_vram.vhd":74:4:74:15|Tristate driver monitoring_o_10 on net monitoring_o_10 has its enable tied to GND (module gdp_vram) @W: MO111 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_vram.vhd":74:4:74:15|Tristate driver monitoring_o_11 on net monitoring_o_11 has its enable tied to GND (module gdp_vram) @W: MO111 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_vram.vhd":74:4:74:15|Tristate driver monitoring_o_12 on net monitoring_o_12 has its enable tied to GND (module gdp_vram) @W: MO111 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_vram.vhd":74:4:74:15|Tristate driver monitoring_o_13 on net monitoring_o_13 has its enable tied to GND (module gdp_vram) @W: MO111 :|Tristate driver monitoring_o_t[3] on net monitoring_o[3] has its enable tied to GND (module gdp_top) @W: MO111 :|Tristate driver monitoring_o_t[4] on net monitoring_o[4] has its enable tied to GND (module gdp_top) @W: MO111 :|Tristate driver monitoring_o_t[5] on net monitoring_o[5] has its enable tied to GND (module gdp_top) @W: MO111 :|Tristate driver monitoring_o_t[6] on net monitoring_o[6] has its enable tied to GND (module gdp_top) @W: MO111 :|Tristate driver monitoring_o_t[7] on net monitoring_o[7] has its enable tied to GND (module gdp_top) @W: MO111 :|Tristate driver monitoring_o_t[8] on net monitoring_o[8] has its enable tied to GND (module gdp_top) @W: MO111 :|Tristate driver monitoring_o_t[9] on net monitoring_o[9] has its enable tied to GND (module gdp_top) @W: MO111 :|Tristate driver monitoring_o_t[10] on net monitoring_o[10] has its enable tied to GND (module gdp_top) @W: MO111 :|Tristate driver monitoring_o_t[11] on net monitoring_o[11] has its enable tied to GND (module gdp_top) @W: MO111 :|Tristate driver monitoring_o_t[12] on net monitoring_o[12] has its enable tied to GND (module gdp_top) @W: MO111 :|Tristate driver monitoring_o_t[13] on net monitoring_o[13] has its enable tied to GND (module gdp_top) @W: MO111 :|Tristate driver monitoring_o_t[14] on net monitoring_o[14] has its enable tied to GND (module gdp_top) @W: MO111 :|Tristate driver monitoring_o_t[15] on net monitoring_o[15] has its enable tied to GND (module gdp_top) @W: MO111 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\ps2_stuff\ps2keyboard.vhd":55:4:55:15|Tristate driver monitoring_o_1 on net monitoring_o_1 has its enable tied to GND (module PS2Keyboard) @W: MO111 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\ps2_stuff\ps2keyboard.vhd":55:4:55:15|Tristate driver monitoring_o_2 on net monitoring_o_2 has its enable tied to GND (module PS2Keyboard) @W: MO111 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\ps2_stuff\ps2keyboard.vhd":55:4:55:15|Tristate driver monitoring_o_3 on net monitoring_o_3 has its enable tied to GND (module PS2Keyboard) @W: MO111 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\ps2_stuff\ps2keyboard.vhd":55:4:55:15|Tristate driver monitoring_o_4 on net monitoring_o_4 has its enable tied to GND (module PS2Keyboard) @W: MO111 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\ps2_stuff\ps2keyboard.vhd":55:4:55:15|Tristate driver monitoring_o_5 on net monitoring_o_5 has its enable tied to GND (module PS2Keyboard) @W: MO111 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\ps2_stuff\ps2keyboard.vhd":55:4:55:15|Tristate driver monitoring_o_6 on net monitoring_o_6 has its enable tied to GND (module PS2Keyboard) @W: MO111 :|Tristate driver monitoring_o_t[3] on net monitoring_o[3] has its enable tied to GND (module gdp_lattice_top) @W: MO111 :|Tristate driver monitoring_o_t[4] on net monitoring_o[4] has its enable tied to GND (module gdp_lattice_top) @W: MO111 :|Tristate driver monitoring_o_t[5] on net monitoring_o[5] has its enable tied to GND (module gdp_lattice_top) @W: MO111 :|Tristate driver monitoring_o_t[6] on net monitoring_o[6] has its enable tied to GND (module gdp_lattice_top) @W: MO111 :|Tristate driver monitoring_o_t[7] on net monitoring_o[7] has its enable tied to GND (module gdp_lattice_top) @W: MO111 :|Tristate driver monitoring_o_t[8] on net monitoring_o[8] has its enable tied to GND (module gdp_lattice_top) @W: MO111 :|Tristate driver monitoring_o_t[9] on net monitoring_o[9] has its enable tied to GND (module gdp_lattice_top) @W: MO111 :|Tristate driver monitoring_o_t[10] on net monitoring_o[10] has its enable tied to GND (module gdp_lattice_top) @W: MO111 :|Tristate driver monitoring_o_t[11] on net monitoring_o[11] has its enable tied to GND (module gdp_lattice_top) @W: MO111 :|Tristate driver monitoring_o_t[12] on net monitoring_o[12] has its enable tied to GND (module gdp_lattice_top) @W: MO111 :|Tristate driver monitoring_o_t[13] on net monitoring_o[13] has its enable tied to GND (module gdp_lattice_top) @W: MO111 :|Tristate driver monitoring_o_t[14] on net monitoring_o[14] has its enable tied to GND (module gdp_lattice_top) @W: MO111 :|Tristate driver monitoring_o_t[15] on net monitoring_o[15] has its enable tied to GND (module gdp_lattice_top) @N: BN362 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\sound\wf2149ip_top_soc.vhd":123:8:123:9|Removing sequential instance impl_sound\.Sound_inst.PORT_B[7:0] of view:PrimLib.dffre(prim) in hierarchy view:work.gdp_lattice_top(rtl) because there are no references to its outputs @N: BN362 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\sound\wf2149ip_top_soc.vhd":123:8:123:9|Removing sequential instance impl_sound\.Sound_inst.PORT_A[7:0] of view:PrimLib.dffre(prim) in hierarchy view:work.gdp_lattice_top(rtl) because there are no references to its outputs @N: BN362 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\sound\wf2149ip_top_soc.vhd":67:8:67:9|Removing sequential instance impl_sound\.Sound_inst.P_WAVSTRB\.tmp of view:PrimLib.dffre(prim) in hierarchy view:work.gdp_lattice_top(rtl) because there are no references to its outputs Available hyper_sources - for debug and ip models None Found @N: FX493 |Applying initial value "111111111" on instance GDPHS.GDP.video.use_clut.clut_inst.clut_1[8:0] @N: FX493 |Applying initial value "000000000" on instance GDPHS.GDP.video.use_clut.clut_inst.clut_0[8:0] @N: FX493 |Applying initial value "00" on instance GDPHS.sync_reset.reset_sync.sync_resetŪreset_syncŪtmp_v[1:0] @N: FX493 |Applying initial value "00000000" on instance GDPHS.GDP.color_reg[7:0] @N: FA239 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_kernel.vhd":407:4:407:17|ROM cdx[6:0] mapped in logic. @N: FA239 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_kernel.vhd":407:4:407:17|ROM cdx[6:0] mapped in logic. @N: MO106 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_kernel.vhd":407:4:407:17|Found ROM, 'cdx[6:0]', 15 words by 7 bits @N: FA239 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\ser\ser1.vhd":281:34:281:50|ROM un10_baud_cnt[10:0] mapped in logic. @N: FA239 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\ser\ser1.vhd":281:34:281:50|ROM un10_baud_cnt[10:0] mapped in logic. @N: MO106 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\ser\ser1.vhd":281:34:281:50|Found ROM, 'un10_baud_cnt[10:0]', 16 words by 11 bits @N: FA239 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\sound\wf2149ip_wave.vhd":461:36:461:40|ROM VOLUME_C[7:0] mapped in logic. @N: FA239 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\sound\wf2149ip_wave.vhd":427:36:427:40|ROM VOLUME_B[7:0] mapped in logic. @N: FA239 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\sound\wf2149ip_wave.vhd":393:36:393:40|ROM VOLUME_A[7:0] mapped in logic. @N: FA239 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\sound\wf2149ip_wave.vhd":461:36:461:40|ROM VOLUME_C[7:0] mapped in logic. @N: MO106 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\sound\wf2149ip_wave.vhd":461:36:461:40|Found ROM, 'VOLUME_C[7:0]', 31 words by 8 bits @N: FA239 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\sound\wf2149ip_wave.vhd":427:36:427:40|ROM VOLUME_B[7:0] mapped in logic. @N: MO106 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\sound\wf2149ip_wave.vhd":427:36:427:40|Found ROM, 'VOLUME_B[7:0]', 31 words by 8 bits @N: FA239 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\sound\wf2149ip_wave.vhd":393:36:393:40|ROM VOLUME_A[7:0] mapped in logic. @N: MO106 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\sound\wf2149ip_wave.vhd":393:36:393:40|Found ROM, 'VOLUME_A[7:0]', 31 words by 8 bits Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 143MB) @N: BN362 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_bi.vhd":93:4:93:5|Removing sequential instance bi_inst.addr_o[7] in hierarchy view:work.gdp_lattice_top(rtl) because there are no references to its outputs @N: BN362 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_bi.vhd":93:4:93:5|Removing sequential instance bi_inst.addr_o[6] in hierarchy view:work.gdp_lattice_top(rtl) because there are no references to its outputs @N: BN362 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_bi.vhd":93:4:93:5|Removing sequential instance bi_inst.addr_o[5] in hierarchy view:work.gdp_lattice_top(rtl) because there are no references to its outputs @N: BN362 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_bi.vhd":93:4:93:5|Removing sequential instance bi_inst.addr_o[4] in hierarchy view:work.gdp_lattice_top(rtl) because there are no references to its outputs @N: BN362 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_bi.vhd":93:4:93:5|Removing sequential instance bi_inst.addr_o[3] in hierarchy view:work.gdp_lattice_top(rtl) because there are no references to its outputs @N:"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_top.vhd":417:4:417:5|Found counter in view:work.gdp_lattice_top(rtl) inst GDP.clut_addr[3:0] Encoding state machine rd_state[0:3] (netlist:statemachine) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 Encoding state machine state[0:4] (netlist:statemachine) original code -> new code 00001 -> 00001 00010 -> 00010 00100 -> 00100 01000 -> 01000 10000 -> 10000 @N:"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_kernel.vhd":365:4:365:5|Found counter in view:work.gdp_kernel(rtl) inst q[24:0] @N: FX404 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_kernel.vhd":508:4:508:7|Found addmux in view:work.gdp_kernel(rtl) inst kernel_addr_o[15:0] from un1_cached_kernel_addr_1[15:0] Encoding state machine drawCmd[0:4] (netlist:statemachine) original code -> new code 00001 -> 00001 00010 -> 00010 00100 -> 00100 01000 -> 01000 10000 -> 10000 Encoding state machine state[0:4] (netlist:statemachine) original code -> new code 00001 -> 00001 00010 -> 00010 00100 -> 00100 01000 -> 01000 10000 -> 10000 @N:"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_bresenham.vhd":133:6:133:7|Found updn counter in view:work.gdp_bresenham(rtl) inst posx[11:0] @N:"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_bresenham.vhd":133:6:133:7|Found updn counter in view:work.gdp_bresenham(rtl) inst posy[11:0] @N:"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_bresenham.vhd":133:6:133:7|Found counter in view:work.gdp_bresenham(rtl) inst linestyle_count[3:0] @N: FX404 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_bresenham.vhd":324:25:324:33|Found addmux in view:work.gdp_bresenham(rtl) inst fsm_comb\.next_einc_5_s0[10:1] from fsm_comb\.next_einc_5_d1[10:1] @N: FX404 :"c:\program files\lattice\diamond2.0\diamond\2.0\synpbase\lib\vhd\numeric.vhd":903:2:903:3|Found addmux in view:work.gdp_bresenham(rtl) inst fsm_comb\.resize\.inf_abs1[9:0] from inf_abs1_a_1[10:1] @N: FX404 :"c:\program files\lattice\diamond2.0\diamond\2.0\synpbase\lib\vhd\numeric.vhd":903:2:903:3|Found addmux in view:work.gdp_bresenham(rtl) inst fsm_comb\.resize\.inf_abs0[9:0] from inf_abs0_a_0[10:1] @N: MF179 :|Found 12 bit by 12 bit '==' comparator, 'fsm_comb\.un4_enable_i' @N: MF179 :|Found 12 bit by 12 bit '==' comparator, 'fsm_comb\.un8_enable_i' @N: MF179 :|Found 12 bit by 12 bit '==' comparator, 'fsm_comb\.un10_ack_expected' @N: MF179 :|Found 12 bit by 12 bit '==' comparator, 'fsm_comb\.un16_ack_expected' Encoding state machine state[0:3] (netlist:statemachine) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N: FX702 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_font_ram.vhd":23:9:23:12|Found startup values on RAM instance use_int_romŪchar_rom.iram[7:0] @N: FX276 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_font_ram.vhd":23:9:23:12|Startup value iram_0_0.INITVAL_00 = 092360C46401013046120547F054240141F0141F014000060000600000000BE00000000000000000 @N: FX276 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_font_ram.vhd":23:9:23:12|Startup value iram_0_0.INITVAL_01 = 0E0B0000000100807C080102A0387F0382A0001C0444100000082220380000007016000005004455 @N: FX276 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_font_ram.vhd":23:9:23:12|Startup value iram_0_0.INITVAL_02 = 08246092490A262000000FE020000007C410823E004040101004000000600C000010080100801000 @N: FX276 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_font_ram.vhd":23:9:23:12|Startup value iram_0_0.INITVAL_03 = 0924900C36092490923600605012110C230092490943C0724508A4508E080FE080100F0664D09241 @N: FX276 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_font_ram.vhd":23:9:23:12|Startup value iram_0_0.INITVAL_04 = 00C090A2010040802822082000281402814028000822202808000000ECB6000000003606C0003C29 @N: FX276 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_font_ram.vhd":23:9:23:12|Startup value iram_0_0.INITVAL_05 = 0127F08249092490FE3E082410827F044410824107C36092490927F0FC09012090FC5E0AA5D0823E @N: FX276 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_font_ram.vhd":23:9:23:12|Startup value iram_0_0.INITVAL_06 = 080400807F08222028080FE3F0804008020000410FE410007F010080107F0F4490924107C0101209 @N: FX276 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_font_ram.vhd":23:9:23:12|Startup value iram_0_0.INITVAL_07 = 04C46052190127F0BC210A24107C06012090127F07C410824107C7F010040047F0FE02018020FE40 @N: FX276 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_font_ram.vhd":23:9:23:12|Startup value iram_0_0.INITVAL_08 = 0E00800E6302808028630FE20030200FE1F040400401F07E400804007E010027F002010644909249 @N: FX276 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_font_ram.vhd":23:9:23:12|Startup value iram_0_0.INITVAL_09 = 10080100801000400401004040007F08241000200200800802000410827F0004308A490A26100E08 @N: FX276 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_font_ram.vhd":23:9:23:12|Startup value iram_0_0.INITVAL_0A = 01000090540A838000400FE440883809044088380003C088440FE40080780A8540E0000000B00E00 @N: FX276 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_font_ram.vhd":23:9:23:12|Startup value iram_0_0.INITVAL_0B = 0807E00400088280207E000000E88008000000000F40000078008040FE000F8A414898000020147C @N: FX276 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_font_ram.vhd":23:9:23:12|Startup value iram_0_0.INITVAL_0C = 00004008080F800100FC0482403018048241F800070440883800078008040F8000F0040F8040F800 @N: FX276 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_font_ram.vhd":23:9:23:12|Startup value iram_0_0.INITVAL_0D = 0401C00044090380484407840060400780C060400600C0807C08040078200883E00800048540A848 @N: FX276 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_font_ram.vhd":23:9:23:12|Startup value iram_0_0.INITVAL_0E = 0AA2A0AA2A0AA04010040040401036082410000000077000000824106C0800004098540C8401F8A0 @N: FX276 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_font_ram.vhd":23:9:23:12|Startup value iram_0_0.INITVAL_0F = 0000000000000000000000000000000000000000000000000000000000F01E0F01E0FF1FEFF1FEFF @N: FX276 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_font_ram.vhd":23:9:23:12|Startup value iram_0_0.INITVAL_10 = 092360C46401013046120547F054240141F0141F014000060000600000000BE00000000000000000 @N: FX276 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_font_ram.vhd":23:9:23:12|Startup value iram_0_0.INITVAL_11 = 0E0B0000000100807C080102A0387F0382A0001C0444100000082220380000007016000005004455 @N: FX276 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_font_ram.vhd":23:9:23:12|Startup value iram_0_0.INITVAL_12 = 08246092490A262000000FE020000007C410823E004040101004000000600C000010080100801000 @N: FX276 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_font_ram.vhd":23:9:23:12|Startup value iram_0_0.INITVAL_13 = 0924900C36092490923600605012110C230092490943C0724508A4508E080FE080100F0664D09241 @N: FX276 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_font_ram.vhd":23:9:23:12|Startup value iram_0_0.INITVAL_14 = 00C090A2010040802822082000281402814028000822202808000000ECB6000000003606C0003C29 @N: FX276 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_font_ram.vhd":23:9:23:12|Startup value iram_0_0.INITVAL_15 = 0127F08249092490FE3E082410827F044410824107C36092490927F0FC09012090FC5E0AA5D0823E @N: FX276 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_font_ram.vhd":23:9:23:12|Startup value iram_0_0.INITVAL_16 = 080400807F08222028080FE3F0804008020000410FE410007F010080107F0F4490924107C0101209 @N: FX276 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_font_ram.vhd":23:9:23:12|Startup value iram_0_0.INITVAL_17 = 04C46052190127F0BC210A24107C06012090127F07C410824107C7F010040047F0FE02018020FE40 @N: FX276 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_font_ram.vhd":23:9:23:12|Startup value iram_0_0.INITVAL_18 = 0E00800E6302808028630FE20030200FE1F040400401F07E400804007E010027F002010644909249 @N: FX276 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_font_ram.vhd":23:9:23:12|Startup value iram_0_0.INITVAL_19 = 10080100801000400401004040FA40080400FA3D084420843D0FA0A0120A0FA4308A490A26100E08 @N: FX276 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_font_ram.vhd":23:9:23:12|Startup value iram_0_0.INITVAL_1A = 01000090540A838000400FE440883809044088380003C088440FE40080780A8540E0000000B00E00 @N: FX276 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_font_ram.vhd":23:9:23:12|Startup value iram_0_0.INITVAL_1B = 0807E00400088280207E000000E88008000000000F40000078008040FE000F8A414898000020147C @N: FX276 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_font_ram.vhd":23:9:23:12|Startup value iram_0_0.INITVAL_1C = 00004008080F800100FC0482403018048241F800070440883800078008040F8000F0040F8040F800 @N: FX276 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_font_ram.vhd":23:9:23:12|Startup value iram_0_0.INITVAL_1D = 0401C00044090380484407840060400780C060400600C0807C08040078200883E00800048540A848 @N: FX276 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_font_ram.vhd":23:9:23:12|Startup value iram_0_0.INITVAL_1E = 0AA2A0AA2A0AA3209A010FE000807D0804007A390884407200082780A8540E204098540C8401F8A0 @N: FX276 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_font_ram.vhd":23:9:23:12|Startup value iram_0_0.INITVAL_1F = 0000007008010080103801008010080700801008010380100801008000F01E0F01E0FF1FEFF1FEFF @N: FX702 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_font_ram.vhd":23:9:23:12|Found startup values on RAM instance use_int_romŪchar_rom.iram[7:0] @N:"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_character.vhd":198:6:198:7|Found updn counter in view:work.gdp_character(rtl) inst posx[11:0] @N:"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_character.vhd":198:6:198:7|Found counter in view:work.gdp_character(rtl) inst posy[11:0] @N:"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_character.vhd":198:6:198:7|Found counter in view:work.gdp_character(rtl) inst xscnt[3:0] @N:"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_character.vhd":198:6:198:7|Found counter in view:work.gdp_character(rtl) inst ypcnt[3:0] @N:"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_character.vhd":198:6:198:7|Found counter in view:work.gdp_character(rtl) inst yscnt[3:0] Encoding state machine state[0:2] (netlist:statemachine) original code -> new code 00000001 -> 00 00000010 -> 01 00001000 -> 10 Encoding state machine mstate[0:2] (netlist:statemachine) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine tx_state[0:2] (netlist:statemachine) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine rx_state[0:3] (netlist:statemachine) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N: FX404 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\sound\wf2149ip_wave.vhd":200:12:200:13|Found addmux in view:work.WF2149IP_WAVE(behavior) inst NOISEGENERATOR\.cnt_noise_6[4:0] from un1_cnt_noise_2[4:0] @N: FX404 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\sound\wf2149ip_wave.vhd":144:12:144:13|Found addmux in view:work.WF2149IP_WAVE(behavior) inst MUSICGENERATOR\.cnt_ch_a_6[11:0] from un1_cnt_ch_a_2[11:0] @N: FX404 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\sound\wf2149ip_wave.vhd":144:12:144:13|Found addmux in view:work.WF2149IP_WAVE(behavior) inst MUSICGENERATOR\.cnt_ch_b_5[11:0] from un1_cnt_ch_b_2[11:0] @N: FX404 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\sound\wf2149ip_wave.vhd":144:12:144:13|Found addmux in view:work.WF2149IP_WAVE(behavior) inst MUSICGENERATOR\.cnt_ch_c_5[11:0] from un1_cnt_ch_c_2[11:0] @N:"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\timer\timer.vhd":77:6:77:7|Found counter in view:work.Timer(rtl) inst Timer_reg[15:0] @N:"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\timer\timer.vhd":77:6:77:7|Found counter in view:work.Timer(rtl) inst prescaler[5:0] Encoding state machine kbd_init_state[0:2] (netlist:statemachine) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine fetch_state[0:3] (netlist:statemachine) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N: FX404 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\ps2_stuff\ps2_decoder.vhd":322:6:322:9|Found addmux in view:work.PS2_Decoder(rtl) inst un1_nkccode_v_0_s0[8:0] from un1_nkccode_v_0_d1[8:0] Encoding state machine state[0:4] (netlist:statemachine) original code -> new code 00001 -> 00001 00010 -> 00010 00100 -> 00100 01000 -> 01000 10000 -> 10000 @N:"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\ps2_stuff\ps2_interface.vhd":167:4:167:5|Found counter in view:work.PS2_Interface_PS2if(rtl) inst q[3:0] @N:"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\ps2_stuff\ps2_interface.vhd":167:4:167:5|Found counter in view:work.PS2_Interface_PS2if(rtl) inst delayCnt[11:0] @W: BN132 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\ps2_stuff\ps2_interface.vhd":167:4:167:5|Removing instance GDPHS.impl_key2.kbd.PS2if.CmdReg[7], because it is equivalent to instance GDPHS.impl_key2.kbd.PS2if.CmdReg[6] @W: BN132 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\ps2_stuff\ps2_interface.vhd":167:4:167:5|Removing instance GDPHS.impl_key2.kbd.PS2if.CmdReg[6], because it is equivalent to instance GDPHS.impl_key2.kbd.PS2if.CmdReg[5] Encoding state machine mouse_state[0:3] (netlist:statemachine) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 Encoding state machine state[0:4] (netlist:statemachine) original code -> new code 00001 -> 00001 00010 -> 00010 00100 -> 00100 01000 -> 01000 10000 -> 10000 @N:"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\ps2_stuff\ps2_interface.vhd":167:4:167:5|Found counter in view:work.PS2_Interface(rtl) inst q[3:0] @N:"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\ps2_stuff\ps2_interface.vhd":167:4:167:5|Found counter in view:work.PS2_Interface(rtl) inst delayCnt[11:0] @W: BN132 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\ps2_stuff\ps2_interface.vhd":167:4:167:5|Removing instance GDPHS.impl_mouse.mouse.PS2if.CmdReg[7], because it is equivalent to instance GDPHS.impl_mouse.mouse.PS2if.CmdReg[6] Encoding state machine state[0:24] (netlist:statemachine) original code -> new code 000000000000000000000000000000000001 -> 0000000000000000000000001 000000000000000000000000000000000010 -> 0000000000000000000000010 000000000000000000000000000000000100 -> 0000000000000000000000100 000000000000000000000000000000001000 -> 0000000000000000000001000 000000000000000000000000000000010000 -> 0000000000000000000010000 000000000000000000000000000000100000 -> 0000000000000000000100000 000000000000000000000000000001000000 -> 0000000000000000001000000 000000000000000000000000000010000000 -> 0000000000000000010000000 000000000000000000000000100000000000 -> 0000000000000000100000000 000000000000000000000001000000000000 -> 0000000000000001000000000 000000000000000000000010000000000000 -> 0000000000000010000000000 000000000000000000000100000000000000 -> 0000000000000100000000000 000000000000000000001000000000000000 -> 0000000000001000000000000 000000000000000000010000000000000000 -> 0000000000010000000000000 000000000000000000100000000000000000 -> 0000000000100000000000000 000000000000001000000000000000000000 -> 0000000001000000000000000 000000000000010000000000000000000000 -> 0000000010000000000000000 000000000000100000000000000000000000 -> 0000000100000000000000000 000000000001000000000000000000000000 -> 0000001000000000000000000 000000000100000000000000000000000000 -> 0000010000000000000000000 000000010000000000000000000000000000 -> 0000100000000000000000000 000000100000000000000000000000000000 -> 0001000000000000000000000 000001000000000000000000000000000000 -> 0010000000000000000000000 010000000000000000000000000000000000 -> 0100000000000000000000000 100000000000000000000000000000000000 -> 1000000000000000000000000 @N: BN362 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_global-p.vhd":57:27:57:27|Removing sequential instance dec.drawCmd[4] in hierarchy view:work.gdp_kernel(rtl) because there are no references to its outputs @N: BN362 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\ps2_stuff\ps2_interface.vhd":167:4:167:5|Removing sequential instance impl_mouse\.mouse.PS2if.ParityError in hierarchy view:work.gdp_lattice_top(rtl) because there are no references to its outputs @N: BN362 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\ps2_stuff\ps2_interface.vhd":167:4:167:5|Removing sequential instance impl_mouse\.mouse.PS2if.ackReceived in hierarchy view:work.gdp_lattice_top(rtl) because there are no references to its outputs @N: BN362 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\ps2_stuff\ps2_interface.vhd":167:4:167:5|Removing sequential instance impl_key2\.kbd.PS2if.ParityError in hierarchy view:work.gdp_lattice_top(rtl) because there are no references to its outputs @N: BN362 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\ps2_stuff\ps2_interface.vhd":167:4:167:5|Removing sequential instance impl_key2\.kbd.PS2if.ackReceived in hierarchy view:work.gdp_lattice_top(rtl) because there are no references to its outputs @N: BN362 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\ser\ser1.vhd":424:6:424:7|Removing sequential instance impl_ser1\.ser.tx_irq in hierarchy view:work.gdp_lattice_top(rtl) because there are no references to its outputs @N: BN362 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_vram.vhd":257:4:257:5|Removing sequential instance GDP.vram.rd_ack_o in hierarchy view:work.gdp_lattice_top(rtl) because there are no references to its outputs Finished factoring (Time elapsed 0h:00m:02s; Memory used current: 181MB peak: 182MB) @N: BN362 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\gdp_vram.vhd":257:4:257:5|Removing sequential instance GDPHS.GDP.vram.kernel_ack_o in hierarchy view:work.gdp_fpgaii_top(rtl) because there are no references to its outputs @N: BN362 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gide.vhd":128:2:128:3|Removing sequential instance GIDE1.D_WR_EN in hierarchy view:work.gdp_fpgaii_top(rtl) because there are no references to its outputs #################### START OF GENERATED CLOCK OPTIMIZATION REPORT ####################[ ====================================================================================== Instance:Pin Generated Clock Optimization Status ====================================================================================== GIDE1.state[14]:C Done GIDE1.state[15]:C Done GIDE1.state[16]:C Done GIDE1.state[17]:C Done GIDE1.state[18]:C Done GIDE1.state[19]:C Done GIDE1.state[20]:C Done GIDE1.state[21]:C Done GIDE1.state[22]:C Done GIDE1.state[23]:C Done GIDE1.state[24]:C Done GIDE1.state[0]:C Done GIDE1.state[1]:C Done GIDE1.state[2]:C Done GIDE1.state[3]:C Done GIDE1.state[4]:C Done GIDE1.state[5]:C Done GIDE1.state[6]:C Done GIDE1.state[7]:C Done GIDE1.state[8]:C Done GIDE1.state[9]:C Done GIDE1.state[10]:C Done GIDE1.state[11]:C Done GIDE1.state[12]:C Done GIDE1.state[13]:C Done GIDE1.D_WR_LOW_HIGH:C Done GIDE1.IDE_WR_EN:C Done GIDE1.IDE_WR_SIG:C Done GIDE1.TOGGLE:C Done GIDE1.IDE_RD_SIG:C Done GIDE1.CS_BUFFER[1]:C Done GIDE1.CS_BUFFER[0]:C Done GIDE1.ADR_BUFFER[2]:C Done GIDE1.ADR_BUFFER[1]:C Done GIDE1.ADR_BUFFER[0]:C Done GIDE1.DATA_IDE_D[15]:C Done GIDE1.DATA_IDE_D[14]:C Done GIDE1.DATA_IDE_D[13]:C Done GIDE1.DATA_IDE_D[12]:C Done GIDE1.DATA_IDE_D[11]:C Done GIDE1.DATA_IDE_D[10]:C Done GIDE1.DATA_IDE_D[9]:C Done GIDE1.DATA_IDE_D[8]:C Done GIDE1.DATA_IDE_D[7]:C Done GIDE1.DATA_IDE_D[6]:C Done GIDE1.DATA_IDE_D[5]:C Done GIDE1.DATA_IDE_D[4]:C Done GIDE1.DATA_IDE_D[3]:C Done GIDE1.DATA_IDE_D[2]:C Done GIDE1.DATA_IDE_D[1]:C Done GIDE1.DATA_IDE_D[0]:C Done GIDE1.gide_wbs_ack:C Done GIDE1.DATA_D_IDE[15]:C Done GIDE1.DATA_D_IDE[14]:C Done GIDE1.DATA_D_IDE[13]:C Done GIDE1.DATA_D_IDE[12]:C Done GIDE1.DATA_D_IDE[11]:C Done GIDE1.DATA_D_IDE[10]:C Done GIDE1.DATA_D_IDE[9]:C Done GIDE1.DATA_D_IDE[8]:C Done GIDE1.DATA_D_IDE[7]:C Done GIDE1.DATA_D_IDE[6]:C Done GIDE1.DATA_D_IDE[5]:C Done GIDE1.DATA_D_IDE[4]:C Done GIDE1.DATA_D_IDE[3]:C Done GIDE1.DATA_D_IDE[2]:C Done GIDE1.DATA_D_IDE[1]:C Done GIDE1.DATA_D_IDE[0]:C Done ##################### END OF GENERATED CLOCK OPTIMIZATION REPORT #####################] Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:02s; Memory used current: 169MB peak: 184MB) Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:03s; Memory used current: 160MB peak: 184MB) @N: FX211 |Packed ROM GDPHS.impl_key2\.kbd.PS2dec.p_lookup\.LookupData_1_0[7:0] (9 input, 8 output) to Block SelectRAM @N: FX404 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\ps2_stuff\ps2_decoder.vhd":322:6:322:9|Found addmux in view:work.gdp_fpgaii_top(rtl) inst GDPHS.impl_key2\.kbd.PS2dec.next_LookupAddress_23_0[8:0] from GDPHS.impl_key2\.kbd.PS2dec.un1_nkccode_v[8:0] Starting Early Timing Optimization (Time elapsed 0h:00m:04s; Memory used current: 159MB peak: 184MB) Finished Early Timing Optimization (Time elapsed 0h:00m:10s; Memory used current: 202MB peak: 202MB) Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:10s; Memory used current: 200MB peak: 203MB) Finished preparing to map (Time elapsed 0h:00m:11s; Memory used current: 202MB peak: 203MB) Finished technology mapping (Time elapsed 0h:00m:14s; Memory used current: 229MB peak: 238MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:14s -8.78ns 2611 / 1367 2 0h:00m:14s -8.78ns 2612 / 1367 3 0h:00m:14s -8.78ns 2612 / 1367 4 0h:00m:14s -8.78ns 2612 / 1367 ------------------------------------------------------------ Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:15s -8.41ns 2640 / 1353 2 0h:00m:15s -8.41ns 2640 / 1353 3 0h:00m:15s -8.41ns 2640 / 1353 4 0h:00m:15s -8.41ns 2640 / 1353 ------------------------------------------------------------ Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:16s -8.41ns 2684 / 1353 2 0h:00m:16s -8.41ns 2682 / 1353 3 0h:00m:16s -8.41ns 2682 / 1353 4 0h:00m:16s -8.41ns 2682 / 1353 5 0h:00m:16s -8.41ns 2682 / 1353 6 0h:00m:16s -8.41ns 2682 / 1353 ------------------------------------------------------------ Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:16s; Memory used current: 186MB peak: 238MB) @N: FX164 |The option to pack flops in the IOB has not been specified Finished restoring hierarchy (Time elapsed 0h:00m:17s; Memory used current: 191MB peak: 238MB) Writing Analyst data base D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGAII\GDPFPGAII\GDPFPGAII_GDPFPGAII.srm Finished Writing Netlist Databases (Time elapsed 0h:00m:17s; Memory used current: 190MB peak: 238MB) Writing EDIF Netlist and constraint files F-2012.03L-1 Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:18s; Memory used current: 197MB peak: 238MB) Starting Writing Gated Clock Conversion Report (Time elapsed 0h:00m:18s; Memory used current: 187MB peak: 238MB) ================= Gated clock report ================= The following instances have NOT been converted Seq Inst Instance Port Clock Reason for not converting ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- GDPHS.GDP.vram.sram_data_i_tmp[15] CK GDPHS.GDP.vram.mstate_c[2] Gating structure creates Improper Gating Logic. See the Gated Clocks description in the user guide for conversion requirements. GDPHS.GDP.vram.sram_data_i_tmp[14] CK GDPHS.GDP.vram.mstate_c[2] Gating structure creates Improper Gating Logic. See the Gated Clocks description in the user guide for conversion requirements. GDPHS.GDP.vram.sram_data_i_tmp[13] CK GDPHS.GDP.vram.mstate_c[2] Gating structure creates Improper Gating Logic. See the Gated Clocks description in the user guide for conversion requirements. GDPHS.GDP.vram.sram_data_i_tmp[12] CK GDPHS.GDP.vram.mstate_c[2] Gating structure creates Improper Gating Logic. See the Gated Clocks description in the user guide for conversion requirements. GDPHS.GDP.vram.sram_data_i_tmp[11] CK GDPHS.GDP.vram.mstate_c[2] Gating structure creates Improper Gating Logic. See the Gated Clocks description in the user guide for conversion requirements. GDPHS.GDP.vram.sram_data_i_tmp[10] CK GDPHS.GDP.vram.mstate_c[2] Gating structure creates Improper Gating Logic. See the Gated Clocks description in the user guide for conversion requirements. GDPHS.GDP.vram.sram_data_i_tmp[9] CK GDPHS.GDP.vram.mstate_c[2] Gating structure creates Improper Gating Logic. See the Gated Clocks description in the user guide for conversion requirements. GDPHS.GDP.vram.sram_data_i_tmp[8] CK GDPHS.GDP.vram.mstate_c[2] Gating structure creates Improper Gating Logic. See the Gated Clocks description in the user guide for conversion requirements. GDPHS.GDP.vram.sram_data_i_tmp[7] CK GDPHS.GDP.vram.mstate_c[2] Gating structure creates Improper Gating Logic. See the Gated Clocks description in the user guide for conversion requirements. GDPHS.GDP.vram.sram_data_i_tmp[6] CK GDPHS.GDP.vram.mstate_c[2] Gating structure creates Improper Gating Logic. See the Gated Clocks description in the user guide for conversion requirements. GDPHS.GDP.vram.sram_data_i_tmp[5] CK GDPHS.GDP.vram.mstate_c[2] Gating structure creates Improper Gating Logic. See the Gated Clocks description in the user guide for conversion requirements. GDPHS.GDP.vram.sram_data_i_tmp[4] CK GDPHS.GDP.vram.mstate_c[2] Gating structure creates Improper Gating Logic. See the Gated Clocks description in the user guide for conversion requirements. GDPHS.GDP.vram.sram_data_i_tmp[3] CK GDPHS.GDP.vram.mstate_c[2] Gating structure creates Improper Gating Logic. See the Gated Clocks description in the user guide for conversion requirements. GDPHS.GDP.vram.sram_data_i_tmp[2] CK GDPHS.GDP.vram.mstate_c[2] Gating structure creates Improper Gating Logic. See the Gated Clocks description in the user guide for conversion requirements. GDPHS.GDP.vram.sram_data_i_tmp[1] CK GDPHS.GDP.vram.mstate_c[2] Gating structure creates Improper Gating Logic. See the Gated Clocks description in the user guide for conversion requirements. GDPHS.GDP.vram.sram_data_i_tmp[0] CK GDPHS.GDP.vram.mstate_c[2] Gating structure creates Improper Gating Logic. See the Gated Clocks description in the user guide for conversion requirements. ======================================================================================================================================================================================================================= ================= End gated clock report ================= Finished Writing Gated Clock Conversion Report (Time elapsed 0h:00m:18s; Memory used current: 187MB peak: 238MB) Starting Writing Generated Clock Conversion Report (Time elapsed 0h:00m:18s; Memory used current: 187MB peak: 238MB) @N: MF333 |Generated clock conversion enabled, but no generated clocks found in design Finished Writing Generated Clock Conversion Report (Time elapsed 0h:00m:18s; Memory used current: 187MB peak: 238MB) @W: MT246 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\fpga_specific\ps2_fifo.vhd":297:4:297:10|Blackbox AGEB2 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W: MT246 :"d:\projects\ndr\ndr2.0\eagle\gdp-fpgaii 1.x\software\gdp_fpgaii\gdpfpgaii\vhdl\gdp64hsfpga\rtl\fpga_specific\ps2_fifo.vhd":284:4:284:10|Blackbox ALEB2 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W: MT420 |Found inferred clock gdp_fpgaii_top|clk_i with period 5.00ns. Please declare a user-defined clock on object "p:clk_i" Found clock gdp_vram|mstate_derived_clock[2] with period 5.00ns ##### START OF TIMING REPORT #####[ # Timing Report written on Tue Feb 24 14:41:48 2015 # Top view: gdp_fpgaii_top Requested Frequency: 200.0 MHz Wire load mode: top Paths requested: 3 Constraint File(s): @N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing. Performance Summary ******************* Worst slack in design: -9.407 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group -------------------------------------------------------------------------------------------------------------------------------------------------------------------- gdp_fpgaii_top|clk_i 200.0 MHz 69.4 MHz 5.000 14.407 -9.407 inferred Inferred_clkgroup_0 gdp_vram|mstate_derived_clock[2] 200.0 MHz 488.8 MHz 5.000 2.046 2.954 derived (from gdp_fpgaii_top|clk_i) Inferred_clkgroup_0 System 200.0 MHz 1696.9 MHz 5.000 0.589 -6.267 system system_clkgroup ==================================================================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------------------------------------ Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------------------------------------------------------ System System | 5.000 -6.267 | No paths - | No paths - | No paths - System gdp_fpgaii_top|clk_i | 5.000 -6.697 | No paths - | No paths - | No paths - System gdp_vram|mstate_derived_clock[2] | 5.000 3.832 | No paths - | 5.000 3.832 | No paths - gdp_fpgaii_top|clk_i System | 5.000 -6.136 | No paths - | No paths - | No paths - gdp_fpgaii_top|clk_i gdp_fpgaii_top|clk_i | 5.000 -9.407 | No paths - | No paths - | No paths - gdp_vram|mstate_derived_clock[2] System | No paths - | No paths - | No paths - | 5.000 -1.234 gdp_vram|mstate_derived_clock[2] gdp_fpgaii_top|clk_i | 5.000 2.954 | No paths - | No paths - | No paths - ============================================================================================================================================================ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* Input Ports: Port Starting User Arrival Required Name Reference Constraint Time Time Slack Clock ---------------------------------------------------------------------------------------- CTS_i System (rising) NA 0.000 3.242 3.242 IDE_D[0] System (rising) NA 0.000 2.875 2.875 IDE_D[1] System (rising) NA 0.000 2.875 2.875 IDE_D[2] System (rising) NA 0.000 2.875 2.875 IDE_D[3] System (rising) NA 0.000 2.875 2.875 IDE_D[4] System (rising) NA 0.000 2.875 2.875 IDE_D[5] System (rising) NA 0.000 2.875 2.875 IDE_D[6] System (rising) NA 0.000 2.875 2.875 IDE_D[7] System (rising) NA 0.000 2.875 2.875 IDE_D[8] System (rising) NA 0.000 2.875 2.875 IDE_D[9] System (rising) NA 0.000 2.875 2.875 IDE_D[10] System (rising) NA 0.000 2.875 2.875 IDE_D[11] System (rising) NA 0.000 2.875 2.875 IDE_D[12] System (rising) NA 0.000 2.875 2.875 IDE_D[13] System (rising) NA 0.000 2.875 2.875 IDE_D[14] System (rising) NA 0.000 2.875 2.875 IDE_D[15] System (rising) NA 0.000 2.875 2.875 IDE_INT NA NA NA NA NA LDS_SIZ1_i System (rising) NA 0.000 0.636 0.636 Ps2Clk_io System (rising) NA 0.000 3.832 3.832 Ps2Dat_io System (rising) NA 0.000 2.875 2.875 Ps2MouseClk_io System (rising) NA 0.000 3.832 3.832 Ps2MouseDat_io System (rising) NA 0.000 2.875 2.875 RxD_i System (rising) NA 0.000 3.242 3.242 SD_MISO_i System (rising) NA 0.000 3.168 3.168 SRAM_DB[0] System (rising) NA 0.000 3.832 3.832 SRAM_DB[1] System (rising) NA 0.000 3.832 3.832 SRAM_DB[2] System (rising) NA 0.000 3.832 3.832 SRAM_DB[3] System (rising) NA 0.000 3.832 3.832 SRAM_DB[4] System (rising) NA 0.000 3.832 3.832 SRAM_DB[5] System (rising) NA 0.000 3.832 3.832 SRAM_DB[6] System (rising) NA 0.000 3.832 3.832 SRAM_DB[7] System (rising) NA 0.000 3.832 3.832 SRAM_DB[8] System (rising) NA 0.000 3.832 3.832 SRAM_DB[9] System (rising) NA 0.000 3.832 3.832 SRAM_DB[10] System (rising) NA 0.000 3.832 3.832 SRAM_DB[11] System (rising) NA 0.000 3.832 3.832 SRAM_DB[12] System (rising) NA 0.000 3.832 3.832 SRAM_DB[13] System (rising) NA 0.000 3.832 3.832 SRAM_DB[14] System (rising) NA 0.000 3.832 3.832 SRAM_DB[15] System (rising) NA 0.000 3.832 3.832 UDS_SIZ0_i System (rising) NA 0.000 0.562 0.562 clk_i System (rising) NA 0.000 -1.748 -1.748 nkc_ADDR_i[0] System (rising) NA 0.000 -6.265 -6.265 nkc_ADDR_i[1] System (rising) NA 0.000 -6.534 -6.534 nkc_ADDR_i[2] System (rising) NA 0.000 -6.563 -6.563 nkc_ADDR_i[3] System (rising) NA 0.000 -6.687 -6.687 nkc_ADDR_i[4] System (rising) NA 0.000 -6.546 -6.546 nkc_ADDR_i[5] System (rising) NA 0.000 -6.647 -6.647 nkc_ADDR_i[6] System (rising) NA 0.000 -6.697 -6.697 nkc_ADDR_i[7] System (rising) NA 0.000 -6.540 -6.540 nkc_ADDR_i[8] System (rising) NA 0.000 2.211 2.211 nkc_ADDR_i[9] System (rising) NA 0.000 2.211 2.211 nkc_ADDR_i[10] System (rising) NA 0.000 2.211 2.211 nkc_ADDR_i[11] System (rising) NA 0.000 2.211 2.211 nkc_ADDR_i[12] System (rising) NA 0.000 2.211 2.211 nkc_ADDR_i[13] System (rising) NA 0.000 2.211 2.211 nkc_ADDR_i[14] System (rising) NA 0.000 2.211 2.211 nkc_ADDR_i[15] System (rising) NA 0.000 2.211 2.211 nkc_ADDR_i[16] System (rising) NA 0.000 2.211 2.211 nkc_ADDR_i[17] System (rising) NA 0.000 2.211 2.211 nkc_ADDR_i[18] System (rising) NA 0.000 2.286 2.286 nkc_ADDR_i_020_A0 System (rising) NA 0.000 0.562 0.562 nkc_ADDR_i_020_A1 System (rising) NA 0.000 2.286 2.286 nkc_DB[0] System (rising) NA 0.000 1.465 1.465 nkc_DB[1] System (rising) NA 0.000 1.465 1.465 nkc_DB[2] System (rising) NA 0.000 1.465 1.465 nkc_DB[3] System (rising) NA 0.000 1.465 1.465 nkc_DB[4] System (rising) NA 0.000 1.143 1.143 nkc_DB[5] System (rising) NA 0.000 1.143 1.143 nkc_DB[6] System (rising) NA 0.000 1.465 1.465 nkc_DB[7] System (rising) NA 0.000 1.465 1.465 nkc_DB[8] System (rising) NA 0.000 1.465 1.465 nkc_DB[9] System (rising) NA 0.000 1.465 1.465 nkc_DB[10] System (rising) NA 0.000 1.465 1.465 nkc_DB[11] System (rising) NA 0.000 1.465 1.465 nkc_DB[12] System (rising) NA 0.000 1.465 1.465 nkc_DB[13] System (rising) NA 0.000 1.465 1.465 nkc_DB[14] System (rising) NA 0.000 1.465 1.465 nkc_DB[15] System (rising) NA 0.000 1.465 1.465 nkc_nIORQ_i System (rising) NA 0.000 -6.647 -6.647 nkc_nMEMRQ_i System (rising) NA 0.000 -5.841 -5.841 nkc_nRD_i System (rising) NA 0.000 0.137 0.137 nkc_nWR_i System (rising) NA 0.000 2.211 2.211 reset_n_i System (rising) NA 0.000 0.343 0.343 ======================================================================================== Output Ports: Port Starting User Arrival Required Name Reference Constraint Time Time Slack Clock --------------------------------------------------------------------------------------------------- Blue_o[0] gdp_fpgaii_top|clk_i (rising) NA 3.270 5.000 1.730 Blue_o[1] gdp_fpgaii_top|clk_i (rising) NA 3.270 5.000 1.730 Blue_o[2] gdp_fpgaii_top|clk_i (rising) NA 3.270 5.000 1.730 Green_o[0] gdp_fpgaii_top|clk_i (rising) NA 3.270 5.000 1.730 Green_o[1] gdp_fpgaii_top|clk_i (rising) NA 3.270 5.000 1.730 Green_o[2] gdp_fpgaii_top|clk_i (rising) NA 3.270 5.000 1.730 Hsync_o gdp_fpgaii_top|clk_i (rising) NA 3.270 5.000 1.730 IDE_CS0 gdp_fpgaii_top|clk_i (rising) NA 3.270 5.000 1.730 IDE_CS1 gdp_fpgaii_top|clk_i (rising) NA 3.270 5.000 1.730 IDE_D[0] gdp_fpgaii_top|clk_i (rising) NA 4.166 5.000 0.834 IDE_D[1] gdp_fpgaii_top|clk_i (rising) NA 4.166 5.000 0.834 IDE_D[2] gdp_fpgaii_top|clk_i (rising) NA 4.166 5.000 0.834 IDE_D[3] gdp_fpgaii_top|clk_i (rising) NA 4.166 5.000 0.834 IDE_D[4] gdp_fpgaii_top|clk_i (rising) NA 4.166 5.000 0.834 IDE_D[5] gdp_fpgaii_top|clk_i (rising) NA 4.166 5.000 0.834 IDE_D[6] gdp_fpgaii_top|clk_i (rising) NA 4.166 5.000 0.834 IDE_D[7] gdp_fpgaii_top|clk_i (rising) NA 4.166 5.000 0.834 IDE_D[8] gdp_fpgaii_top|clk_i (rising) NA 4.166 5.000 0.834 IDE_D[9] gdp_fpgaii_top|clk_i (rising) NA 4.166 5.000 0.834 IDE_D[10] gdp_fpgaii_top|clk_i (rising) NA 4.166 5.000 0.834 IDE_D[11] gdp_fpgaii_top|clk_i (rising) NA 4.166 5.000 0.834 IDE_D[12] gdp_fpgaii_top|clk_i (rising) NA 4.166 5.000 0.834 IDE_D[13] gdp_fpgaii_top|clk_i (rising) NA 4.166 5.000 0.834 IDE_D[14] gdp_fpgaii_top|clk_i (rising) NA 4.166 5.000 0.834 IDE_D[15] gdp_fpgaii_top|clk_i (rising) NA 4.166 5.000 0.834 IDE_IA[0] gdp_fpgaii_top|clk_i (rising) NA 3.270 5.000 1.730 IDE_IA[1] gdp_fpgaii_top|clk_i (rising) NA 3.270 5.000 1.730 IDE_IA[2] gdp_fpgaii_top|clk_i (rising) NA 3.270 5.000 1.730 IDE_RD gdp_fpgaii_top|clk_i (rising) NA 3.270 5.000 1.730 IDE_WR gdp_fpgaii_top|clk_i (rising) NA 3.270 5.000 1.730 IRQ0_o gdp_fpgaii_top|clk_i (rising) NA 3.411 5.000 1.589 IRQ1_o gdp_fpgaii_top|clk_i (rising) NA 6.543 5.000 -1.543 PWM_OUT_o gdp_fpgaii_top|clk_i (rising) NA 3.270 5.000 1.730 Ps2Clk_io gdp_fpgaii_top|clk_i (rising) NA 3.270 5.000 1.730 Ps2Dat_io gdp_fpgaii_top|clk_i (rising) NA 3.270 5.000 1.730 Ps2MouseClk_io gdp_fpgaii_top|clk_i (rising) NA 3.270 5.000 1.730 Ps2MouseDat_io gdp_fpgaii_top|clk_i (rising) NA 3.270 5.000 1.730 RTS_o gdp_fpgaii_top|clk_i (rising) NA 3.650 5.000 1.350 Red_o[0] gdp_fpgaii_top|clk_i (rising) NA 3.270 5.000 1.730 Red_o[1] gdp_fpgaii_top|clk_i (rising) NA 3.270 5.000 1.730 Red_o[2] gdp_fpgaii_top|clk_i (rising) NA 3.270 5.000 1.730 SD_MOSI_o gdp_fpgaii_top|clk_i (rising) NA 3.270 5.000 1.730 SD_SCK_o gdp_fpgaii_top|clk_i (rising) NA 3.453 5.000 1.547 SD_nCS_o[0] gdp_fpgaii_top|clk_i (rising) NA 3.270 5.000 1.730 SD_nCS_o[1] gdp_fpgaii_top|clk_i (rising) NA 3.270 5.000 1.730 SRAM_ADDR[0] gdp_fpgaii_top|clk_i (rising) NA 4.978 5.000 0.022 SRAM_ADDR[1] gdp_fpgaii_top|clk_i (rising) NA 4.978 5.000 0.022 SRAM_ADDR[2] gdp_fpgaii_top|clk_i (rising) NA 4.978 5.000 0.022 SRAM_ADDR[3] gdp_fpgaii_top|clk_i (rising) NA 4.978 5.000 0.022 SRAM_ADDR[4] gdp_fpgaii_top|clk_i (rising) NA 4.978 5.000 0.022 SRAM_ADDR[5] gdp_fpgaii_top|clk_i (rising) NA 4.978 5.000 0.022 SRAM_ADDR[6] gdp_fpgaii_top|clk_i (rising) NA 4.978 5.000 0.022 SRAM_ADDR[7] gdp_fpgaii_top|clk_i (rising) NA 4.978 5.000 0.022 SRAM_ADDR[8] gdp_fpgaii_top|clk_i (rising) NA 4.978 5.000 0.022 SRAM_ADDR[9] gdp_fpgaii_top|clk_i (rising) NA 4.978 5.000 0.022 SRAM_ADDR[10] gdp_fpgaii_top|clk_i (rising) NA 4.978 5.000 0.022 SRAM_ADDR[11] gdp_fpgaii_top|clk_i (rising) NA 4.978 5.000 0.022 SRAM_ADDR[12] gdp_fpgaii_top|clk_i (rising) NA 4.978 5.000 0.022 SRAM_ADDR[13] gdp_fpgaii_top|clk_i (rising) NA 4.978 5.000 0.022 SRAM_ADDR[14] gdp_fpgaii_top|clk_i (rising) NA 4.978 5.000 0.022 SRAM_ADDR[15] gdp_fpgaii_top|clk_i (rising) NA 4.978 5.000 0.022 SRAM_ADDR[16] gdp_fpgaii_top|clk_i (rising) NA 4.978 5.000 0.022 SRAM_ADDR[17] NA NA NA NA NA SRAM_DB[0] System (rising) NA 6.748 5.000 -1.748 SRAM_DB[1] System (rising) NA 6.748 5.000 -1.748 SRAM_DB[2] System (rising) NA 6.748 5.000 -1.748 SRAM_DB[3] System (rising) NA 6.748 5.000 -1.748 SRAM_DB[4] System (rising) NA 6.748 5.000 -1.748 SRAM_DB[5] System (rising) NA 6.748 5.000 -1.748 SRAM_DB[6] System (rising) NA 6.748 5.000 -1.748 SRAM_DB[7] System (rising) NA 6.748 5.000 -1.748 SRAM_DB[8] System (rising) NA 6.748 5.000 -1.748 SRAM_DB[9] System (rising) NA 6.748 5.000 -1.748 SRAM_DB[10] System (rising) NA 6.748 5.000 -1.748 SRAM_DB[11] System (rising) NA 6.748 5.000 -1.748 SRAM_DB[12] System (rising) NA 6.748 5.000 -1.748 SRAM_DB[13] System (rising) NA 6.748 5.000 -1.748 SRAM_DB[14] System (rising) NA 6.748 5.000 -1.748 SRAM_DB[15] System (rising) NA 6.748 5.000 -1.748 SRAM_nBHE gdp_fpgaii_top|clk_i (rising) NA 4.978 5.000 0.022 SRAM_nBLE gdp_fpgaii_top|clk_i (rising) NA 4.978 5.000 0.022 SRAM_nCS0 NA NA NA NA NA SRAM_nCS1 NA NA NA NA NA SRAM_nOE NA NA NA NA NA SRAM_nWR NA NA NA NA NA TxD_o gdp_fpgaii_top|clk_i (rising) NA 3.270 5.000 1.730 Vsync_o gdp_fpgaii_top|clk_i (rising) NA 3.411 5.000 1.589 driver_DIR_o System (rising) NA 9.952 5.000 -4.952 driver_nEN_o System (rising) NA 4.657 5.000 0.343 nIRQ_o gdp_fpgaii_top|clk_i (rising) NA 3.650 5.000 1.350 nNMI_o NA NA NA NA NA nkc_DB[0] System (rising) NA 11.201 5.000 -6.201 nkc_DB[1] System (rising) NA 11.068 5.000 -6.068 nkc_DB[2] System (rising) NA 11.267 5.000 -6.267 nkc_DB[3] System (rising) NA 11.134 5.000 -6.134 nkc_DB[4] System (rising) NA 10.612 5.000 -5.612 nkc_DB[5] System (rising) NA 11.068 5.000 -6.068 nkc_DB[6] System (rising) NA 11.259 5.000 -6.259 nkc_DB[7] System (rising) NA 11.068 5.000 -6.068 nkc_DB[8] System (rising) NA 4.547 5.000 0.453 nkc_DB[9] System (rising) NA 4.547 5.000 0.453 nkc_DB[10] System (rising) NA 4.547 5.000 0.453 nkc_DB[11] System (rising) NA 4.547 5.000 0.453 nkc_DB[12] System (rising) NA 4.547 5.000 0.453 nkc_DB[13] System (rising) NA 4.547 5.000 0.453 nkc_DB[14] System (rising) NA 4.547 5.000 0.453 nkc_DB[15] System (rising) NA 4.547 5.000 0.453 nkc_nWAIT_o System (rising) NA 9.288 5.000 -4.288 =================================================================================================== ##### END OF TIMING REPORT #####] --------------------------------------- Resource Usage Report Part: lfxp6c-5 Register bits: 1384 of 5760 (24%) Latch bits: 32 PIC Latch: 16 I/O cells: 140 Block Rams : 2 of 10 (20%) Details: AND2: 4 BB: 52 CB2: 2 CCU2: 319 CU2: 2 DPR16X2B: 4 FADD2: 1 FD1P3AX: 39 FD1P3BX: 83 FD1P3DX: 846 FD1P3IX: 5 FD1S1AY: 16 FD1S3AX: 57 FD1S3BX: 48 FD1S3DX: 276 GSR: 1 IB: 32 IFS1P3BX: 3 IFS1P3DX: 3 IFS1S1B: 16 INV: 36 L6MUX21: 28 OB: 55 OBZ: 1 OFS1P3BX: 10 OFS1P3DX: 5 OFS1P3IX: 9 ORCALUT4: 2649 PDP8KA: 1 PFUMX: 120 PUR: 1 ROM16X1: 2 SP8KA: 1 VHI: 1 VLO: 1 XOR2: 1 false: 35 true: 35 Mapper successful! At Mapper Exit (Time elapsed 0h:00m:18s; Memory used current: 58MB peak: 238MB) Process took 0h:00m:18s realtime, 0h:00m:18s cputime # Tue Feb 24 14:41:48 2015 ###########################################################]