********** Mapped Logic ********** |
B_INT_I <= '0';
B_INT <= B_INT_I when B_INT_OE = '1' else 'Z'; B_INT_OE <= NOT F_INT; |
B_IRQ_I(0) <= '0';
B_IRQ(0) <= B_IRQ_I(0) when B_IRQ_OE(0) = '1' else 'Z'; B_IRQ_OE(0) <= '0'; |
B_IRQ_I(1) <= '0';
B_IRQ(1) <= B_IRQ_I(1) when B_IRQ_OE(1) = '1' else 'Z'; B_IRQ_OE(1) <= '0'; |
B_NMI_I <= '0';
B_NMI <= B_NMI_I when B_NMI_OE = '1' else 'Z'; B_NMI_OE <= '0'; |
B_WAIT_I <= '0';
B_WAIT <= B_WAIT_I when B_WAIT_OE = '1' else 'Z'; B_WAIT_OE <= NOT F_WAIT; |
F_IORQ <= B_IORQ; |
F_MEMRQ <= NOT (((NOT B_MEMRQ AND F_NMI AND B_A(21) AND B_A(20) AND B_A(22))
OR (NOT B_A(29) AND NOT B_A(28) AND NOT B_A(27) AND NOT B_A(26) AND NOT B_A(25) AND NOT B_A(24) AND NOT B_A(23) AND NOT B_MEMRQ AND B_A(21) AND B_A(20) AND B_A(22)))); |
F_RESET <= B_RESET; |
F_SIZ0 <= B_SIZ0; |
F_SIZ1 <= B_SIZ1; |
JP2 <= F_IRQ(0); |
JP3 <= F_NMI; |
JP4 <= ((NOT B_MEMRQ AND F_NMI AND B_A(21) AND B_A(20) AND B_A(22))
OR (NOT B_A(29) AND NOT B_A(28) AND NOT B_A(27) AND NOT B_A(26) AND NOT B_A(25) AND NOT B_A(24) AND NOT B_A(23) AND NOT B_MEMRQ AND B_A(21) AND B_A(20) AND B_A(22))); |
JP5 <= F_IRQ(1); |
Register Legend:
FDCPE (Q,D,C,CLR,PRE); FTCPE (Q,D,C,CLR,PRE); LDCP (Q,D,G,CLR,PRE); |