#Build: Synplify Pro F-2012.03L-1 , Build 063R, May 17 2012
#install: C:\Program Files\lscc\diamond\2.0\synpbase
#OS: Windows 7 6.1
#Hostname: SYNWM9582WM1

#Implementation: GDPFPGAII

$ Start of Compile
#Fri Oct 10 21:51:20 2014

Synopsys VHDL Compiler, version comp201203rcp1, Build 061R, built May 17 2012
@N: :  | Running in 64-bit mode 
Copyright (C) 1994-2012 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.

@N:CD720 : std.vhd(123) | Setting time resolution to ns
@N: : gdp_fpgaii_top.vhd(25) | Top entity is set to gdp_fpgaii_top.
VHDL syntax check successful!
@N:CD630 : gdp_fpgaii_top.vhd(25) | Synthesizing work.gdp_fpgaii_top.rtl 
@W:CD638 : gdp_fpgaii_top.vhd(495) | Signal debug_sig is undriven 
@N:CD630 : sram.vhd(17) | Synthesizing work.sram.sram_1 
Post processing for work.sram.sram_1
@W:CL169 : sram.vhd(64) | Pruning register ws_cnt(20 downto 0)  
@N:CD630 : gide.vhd(26) | Synthesizing work.gide.behavioral 
@N:CD231 : gide.vhd(75) | Using onehot encoding for type state_type (init="100000000000000000000000000000000000")
Post processing for work.gide.behavioral
@W:CL271 : gide.vhd(94) | Pruning bits 4 to 2 of q(4 downto 0) -- not in use ... 
@A:CL282 : gide.vhd(127) | Feedback mux created for signal gide_wbs_ack -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@N:CD630 : gdp_lattice_top.vhd(27) | Synthesizing work.gdp_lattice_top.rtl 
@N:CD367 : gdp_lattice_top.vhd(548) | Instance GDP, Port monitoring_o, Bit <1> connection not specified 
@N:CD367 : gdp_lattice_top.vhd(548) | Instance GDP, Port monitoring_o, Bit <2> connection not specified 
@N:CD367 : gdp_lattice_top.vhd(548) | Instance GDP, Port monitoring_o, Bit <3> connection not specified 
@N:CD367 : gdp_lattice_top.vhd(548) | Instance GDP, Port monitoring_o, Bit <4> connection not specified 
@N:CD367 : gdp_lattice_top.vhd(548) | Instance GDP, Port monitoring_o, Bit <5> connection not specified 
@N:CD367 : gdp_lattice_top.vhd(548) | Instance GDP, Port monitoring_o, Bit <6> connection not specified 
@N:CD367 : gdp_lattice_top.vhd(548) | Instance GDP, Port monitoring_o, Bit <7> connection not specified 
@N:CD367 : gdp_lattice_top.vhd(548) | Instance GDP, Port monitoring_o, Bit <8> connection not specified 
@N:CD367 : gdp_lattice_top.vhd(548) | Instance GDP, Port monitoring_o, Bit <9> connection not specified 
@N:CD367 : gdp_lattice_top.vhd(548) | Instance GDP, Port monitoring_o, Bit <10> connection not specified 
@N:CD367 : gdp_lattice_top.vhd(548) | Instance GDP, Port monitoring_o, Bit <11> connection not specified 
@N:CD367 : gdp_lattice_top.vhd(548) | Instance GDP, Port monitoring_o, Bit <12> connection not specified 
@N:CD367 : gdp_lattice_top.vhd(548) | Instance GDP, Port monitoring_o, Bit <13> connection not specified 
@N:CD367 : gdp_lattice_top.vhd(548) | Instance GDP, Port monitoring_o, Bit <14> connection not specified 
@N:CD367 : gdp_lattice_top.vhd(548) | Instance GDP, Port monitoring_o, Bit <15> connection not specified 
@W:CD638 : gdp_lattice_top.vhd(423) | Signal busyrx is undriven 
@W:CD638 : gdp_lattice_top.vhd(424) | Signal doutparrx is undriven 
@W:CD638 : gdp_lattice_top.vhd(425) | Signal datavalidrx is undriven 
@W:CD638 : gdp_lattice_top.vhd(426) | Signal olddatavalidrx is undriven 
@W:CD638 : gdp_lattice_top.vhd(442) | Signal vdip_cs is undriven 
@W:CD638 : gdp_lattice_top.vhd(443) | Signal vdip_data is undriven 
@W:CD638 : gdp_lattice_top.vhd(452) | Signal q is undriven 
@N:CD630 : Timer.vhd(21) | Synthesizing work.timer.rtl 
Post processing for work.timer.rtl
@W:CL271 : Timer.vhd(77) | Pruning bits 5 to 3 of ctrl_reg(7 downto 0) -- not in use ... 
@N:CD630 : SPI_Interface.vhd(21) | Synthesizing work.spi_interface.rtl 
Post processing for work.spi_interface.rtl
@W:CL265 : SPI_Interface.vhd(94) | Pruning bit 4 of ctrl_reg(7 downto 0) -- not in use ... 
@N:CD630 : wf2149ip_top_soc.vhd(20) | Synthesizing work.wf2149ip_top_soc.structure 
@N:CD233 : wf2149ip_pkg.vhd(20) | Using sequential encoding for type buscycles_t
@N:CD630 : wf2149ip_wave.vhd(21) | Synthesizing work.wf2149ip_wave.behavior 
@N:CD233 : wf2149ip_pkg.vhd(20) | Using sequential encoding for type buscycles_t
@N:CD630 : dac.vhd(28) | Synthesizing work.dac.rtl 
Post processing for work.dac.rtl
Post processing for work.wf2149ip_wave.behavior
@A:CL282 : wf2149ip_wave.vhd(76) | Feedback mux created for signal ENV_RESET -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
Post processing for work.wf2149ip_top_soc.structure
@A:CL282 : wf2149ip_top_soc.vhd(67) | Feedback mux created for signal WAV_STRB -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@N:CD630 : Ser1.vhd(23) | Synthesizing work.ser1.rtl 
@N:CD233 : Ser1.vhd(73) | Using sequential encoding for type tx_state_t
@N:CD233 : Ser1.vhd(106) | Using sequential encoding for type rx_state_t
@W:CD604 : Ser1.vhd(414) | OTHERS clause is not synthesized 
@W:CD604 : Ser1.vhd(562) | OTHERS clause is not synthesized 
@N:CD630 : InputSync-e.vhd(15) | Synthesizing work.inputsync.rtl 
Post processing for work.inputsync.rtl
@N:CD630 : InputSync-e.vhd(15) | Synthesizing work.inputsync.rtl 
Post processing for work.inputsync.rtl
Post processing for work.ser1.rtl
@W:CL190 : Ser1.vhd(196) | Optimizing register bit Status_reg(5) to a constant 0
@W:CL190 : Ser1.vhd(196) | Optimizing register bit Status_reg(7) to a constant 0
@W:CL260 : Ser1.vhd(196) | Pruning register bit 7 of Status_reg(7 downto 0)  
@W:CL260 : Ser1.vhd(196) | Pruning register bit 5 of Status_reg(7 downto 0)  
@N:CD630 : PS2Mouse.vhd(28) | Synthesizing work.ps2mouse.rtl 
@N:CD233 : PS2Mouse.vhd(88) | Using sequential encoding for type mouse_state_t
@N:CD233 : PS2Mouse.vhd(89) | Using sequential encoding for type mouse_send_state_t
@W:CD604 : PS2Mouse.vhd(241) | OTHERS clause is not synthesized 
@W:CD604 : PS2Mouse.vhd(277) | OTHERS clause is not synthesized 
@W:CD604 : PS2Mouse.vhd(280) | OTHERS clause is not synthesized 
@N:CD630 : PS2_Interface.vhd(28) | Synthesizing work.ps2_interface.rtl 
@N:CD233 : PS2_Interface.vhd(67) | Using sequential encoding for type ps2direction_t
@N:CD231 : PS2_Interface.vhd(68) | Using onehot encoding for type state_t (idle="10000")
@N:CD233 : PS2_Interface.vhd(69) | Using sequential encoding for type clkedge_t
Post processing for work.ps2_interface.rtl
Post processing for work.ps2mouse.rtl
@W:CL279 : PS2Mouse.vhd(287) | Pruning register bits 7 to 6 of button_stat(7 downto 0)  
@N:CD630 : PS2Keyboard.vhd(28) | Synthesizing work.ps2keyboard.rtl 
@N:CD233 : PS2Keyboard.vhd(118) | Using sequential encoding for type fifordstate_t
@N:CD233 : PS2Keyboard.vhd(120) | Using sequential encoding for type kbd_init_state_t
@N:CD233 : PS2Keyboard.vhd(121) | Using sequential encoding for type kbd_send_state_t
@W:CD604 : PS2Keyboard.vhd(435) | OTHERS clause is not synthesized 
@W:CD604 : PS2Keyboard.vhd(438) | OTHERS clause is not synthesized 
@W:CD604 : PS2Keyboard.vhd(527) | OTHERS clause is not synthesized 
@W:CD604 : PS2Keyboard.vhd(553) | OTHERS clause is not synthesized 
@W:CD604 : PS2Keyboard.vhd(556) | OTHERS clause is not synthesized 
@N:CD630 : ps2_fifo.vhd(15) | Synthesizing work.ps2_fifo.structure 
@N:CD630 : xp.vhd(1549) | Synthesizing work.rom16x1.syn_black_box 
Post processing for work.rom16x1.syn_black_box
@N:CD630 : xp.vhd(542) | Synthesizing work.fd1p3dx.syn_black_box 
Post processing for work.fd1p3dx.syn_black_box
@N:CD630 : xp.vhd(662) | Synthesizing work.fd1s3bx.syn_black_box 
Post processing for work.fd1s3bx.syn_black_box
@N:CD630 : xp.vhd(673) | Synthesizing work.fd1s3dx.syn_black_box 
Post processing for work.fd1s3dx.syn_black_box
@N:CD630 : xp.vhd(384) | Synthesizing work.dpr16x2b.syn_black_box 
Post processing for work.dpr16x2b.syn_black_box
@N:CD630 : xp.vhd(1643) | Synthesizing work.vlo.syn_black_box 
Post processing for work.vlo.syn_black_box
@N:CD630 : xp.vhd(346) | Synthesizing work.cu2.syn_black_box 
Post processing for work.cu2.syn_black_box
@N:CD630 : xp.vhd(1635) | Synthesizing work.vhi.syn_black_box 
Post processing for work.vhi.syn_black_box
@N:CD630 : xp.vhd(212) | Synthesizing work.ageb2.syn_black_box 
Post processing for work.ageb2.syn_black_box
@N:CD630 : xp.vhd(471) | Synthesizing work.fadd2.syn_black_box 
Post processing for work.fadd2.syn_black_box
@N:CD630 : xp.vhd(224) | Synthesizing work.aleb2.syn_black_box 
Post processing for work.aleb2.syn_black_box
@N:CD630 : xp.vhd(186) | Synthesizing work.cb2.syn_black_box 
Post processing for work.cb2.syn_black_box
@N:CD630 : xp.vhd(236) | Synthesizing work.and2.syn_black_box 
Post processing for work.and2.syn_black_box
@N:CD630 : xp.vhd(989) | Synthesizing work.inv.syn_black_box 
Post processing for work.inv.syn_black_box
@N:CD630 : xp.vhd(1711) | Synthesizing work.xor2.syn_black_box 
Post processing for work.xor2.syn_black_box
Post processing for work.ps2_fifo.structure
@W:CL168 : ps2_fifo.vhd(316) | Pruning instance r_ctr_1 -- not in use ... 
@W:CL168 : ps2_fifo.vhd(305) | Pruning instance w_ctr_1 -- not in use ... 
@W:CL168 : ps2_fifo.vhd(236) | Pruning instance FF_7 -- not in use ... 
@W:CL168 : ps2_fifo.vhd(224) | Pruning instance FF_10 -- not in use ... 
@N:CD630 : PS2_Decoder.vhd(20) | Synthesizing work.ps2_decoder.rtl 
@N:CD233 : PS2_Decoder.vhd(42) | Using sequential encoding for type fetch_state_t
@W:CD604 : PS2_Decoder.vhd(528) | OTHERS clause is not synthesized 
Post processing for work.ps2_decoder.rtl
@W:CL190 : PS2_Decoder.vhd(538) | Optimizing register bit KeyStates(1) to a constant 0
@W:CL260 : PS2_Decoder.vhd(538) | Pruning register bit 1 of KeyStates(7 downto 0)  
Post processing for work.ps2keyboard.rtl
@A:CL282 : PS2Keyboard.vhd(446) | Feedback mux created for signal DataOut_o[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@W:CL111 : PS2Keyboard.vhd(446) | All reachable assignments to KeyOptsReg(2) assign '0'; register removed by optimization
@W:CL111 : PS2Keyboard.vhd(446) | All reachable assignments to KeyOptsReg(3) assign '0'; register removed by optimization
@W:CL111 : PS2Keyboard.vhd(446) | All reachable assignments to KeyOptsReg(4) assign '0'; register removed by optimization
@W:CL111 : PS2Keyboard.vhd(446) | All reachable assignments to KeyOptsReg(5) assign '0'; register removed by optimization
@W:CL111 : PS2Keyboard.vhd(446) | All reachable assignments to KeyOptsReg(6) assign '0'; register removed by optimization
@N:CD630 : gdp_top.vhd(25) | Synthesizing work.gdp_top.rtl 
@N:CD367 : gdp_top.vhd(228) | Instance video, Port monitoring_o, Bit <1> connection not specified 
@N:CD367 : gdp_top.vhd(228) | Instance video, Port monitoring_o, Bit <2> connection not specified 
@N:CD367 : gdp_top.vhd(228) | Instance video, Port monitoring_o, Bit <3> connection not specified 
@N:CD367 : gdp_top.vhd(228) | Instance video, Port monitoring_o, Bit <4> connection not specified 
@N:CD367 : gdp_top.vhd(228) | Instance video, Port monitoring_o, Bit <5> connection not specified 
@N:CD367 : gdp_top.vhd(228) | Instance video, Port monitoring_o, Bit <6> connection not specified 
@N:CD367 : gdp_top.vhd(228) | Instance video, Port monitoring_o, Bit <7> connection not specified 
@W:CD326 : gdp_top.vhd(336) | Port rom_ena_o of entity work.gdp_vram is unconnected
@W:CD796 : gdp_top.vhd(182) | Bit 1 of signal monitoring is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. 
@W:CD796 : gdp_top.vhd(182) | Bit 2 of signal monitoring is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. 
@W:CD796 : gdp_top.vhd(182) | Bit 3 of signal monitoring is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. 
@W:CD796 : gdp_top.vhd(182) | Bit 4 of signal monitoring is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. 
@W:CD796 : gdp_top.vhd(182) | Bit 5 of signal monitoring is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. 
@W:CD796 : gdp_top.vhd(182) | Bit 6 of signal monitoring is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. 
@W:CD796 : gdp_top.vhd(182) | Bit 7 of signal monitoring is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. 
@W:CD796 : gdp_top.vhd(182) | Bit 8 of signal monitoring is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. 
@W:CD796 : gdp_top.vhd(182) | Bit 9 of signal monitoring is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. 
@W:CD796 : gdp_top.vhd(182) | Bit 10 of signal monitoring is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. 
@W:CD796 : gdp_top.vhd(182) | Bit 11 of signal monitoring is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. 
@W:CD796 : gdp_top.vhd(182) | Bit 12 of signal monitoring is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. 
@W:CD796 : gdp_top.vhd(182) | Bit 13 of signal monitoring is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. 
@W:CD796 : gdp_top.vhd(182) | Bit 14 of signal monitoring is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. 
@W:CD796 : gdp_top.vhd(182) | Bit 15 of signal monitoring is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. 
@N:CD630 : gdp_vram.vhd(22) | Synthesizing work.gdp_vram.rtl 
@N:CD233 : gdp_vram.vhd(62) | Using sequential encoding for type state_t
@W:CD604 : gdp_vram.vhd(190) | OTHERS clause is not synthesized 
@W:CD434 : gdp_vram.vhd(87) | Signal ram_address in the sensitivity list is not used in the process
@W:CD434 : gdp_vram.vhd(87) | Signal wr_data in the sensitivity list is not used in the process
@W:CD434 : gdp_vram.vhd(87) | Signal rd_data in the sensitivity list is not used in the process
@W:CD434 : gdp_vram.vhd(87) | Signal ram_wren in the sensitivity list is not used in the process
@W:CD434 : gdp_vram.vhd(88) | Signal kernel_data in the sensitivity list is not used in the process
@W:CD434 : gdp_vram.vhd(89) | Signal chr_rom_addr_i in the sensitivity list is not used in the process
@W:CD434 : gdp_vram.vhd(89) | Signal rom_data in the sensitivity list is not used in the process
@W:CD638 : gdp_vram.vhd(77) | Signal srom_en is undriven 
@W:CD638 : gdp_vram.vhd(79) | Signal srom_req_pend is undriven 
@W:CD638 : gdp_vram.vhd(80) | Signal srom_data is undriven 
Post processing for work.gdp_vram.rtl
@N:CD630 : gdp_kernel.vhd(22) | Synthesizing work.gdp_kernel.rtl 
@N:CD231 : gdp_kernel.vhd(178) | Using onehot encoding for type state_t (idle_e="10000")
@N:CD231 : gdp_global-p.vhd(57) | Using onehot encoding for type drawcmd_t (idle_e="10000")
@W:CD604 : gdp_kernel.vhd(603) | OTHERS clause is not synthesized 
@N:CD630 : gdp_character.vhd(21) | Synthesizing work.gdp_character.rtl 
@N:CD233 : gdp_character.vhd(105) | Using sequential encoding for type char_state_t
@W:CD604 : gdp_character.vhd(446) | OTHERS clause is not synthesized 
@W:CD434 : gdp_character.vhd(271) | Signal rom_busy_i in the sensitivity list is not used in the process
@W:CD434 : gdp_character.vhd(271) | Signal rom_ena in the sensitivity list is not used in the process
@N:CD630 : gdp_font_ram.vhd(8) | Synthesizing work.gdp_font_ram.rtl 
Post processing for work.gdp_font_ram.rtl
@N:CL134 : gdp_font_ram.vhd(23) | Found RAM iram, depth=1024, width=8
Post processing for work.gdp_character.rtl
@W:CL169 : gdp_character.vhd(198) | Pruning register finished  
@W:CL169 : gdp_character.vhd(198) | Pruning register rom_ena  
@N:CD630 : gdp_bresenham.vhd(21) | Synthesizing work.gdp_bresenham.rtl 
@N:CD231 : gdp_bresenham.vhd(72) | Using onehot encoding for type bres_state_t (idle_e="10000")
Post processing for work.gdp_bresenham.rtl
@W:CL190 : gdp_bresenham.vhd(133) | Optimizing register bit edec(0) to a constant 0
@W:CL190 : gdp_bresenham.vhd(133) | Optimizing register bit einc(0) to a constant 0
@W:CL260 : gdp_bresenham.vhd(133) | Pruning register bit 0 of einc(10 downto 0)  
@W:CL260 : gdp_bresenham.vhd(133) | Pruning register bit 0 of edec(10 downto 0)  
@N:CD630 : gdp_decoder.vhd(22) | Synthesizing work.gdp_decoder.rtl 
@N:CD231 : gdp_global-p.vhd(57) | Using onehot encoding for type drawcmd_t (idle_e="10000")
Post processing for work.gdp_decoder.rtl
Post processing for work.gdp_kernel.rtl
@N:CD630 : gdp_video.vhd(23) | Synthesizing work.gdp_video.rtl 
@N:CD233 : gdp_video.vhd(87) | Using sequential encoding for type rd_state_t
@W:CD604 : gdp_video.vhd(279) | OTHERS clause is not synthesized 
@W:CD434 : gdp_video.vhd(218) | Signal rd_address in the sensitivity list is not used in the process
@W:CD434 : gdp_video.vhd(219) | Signal rd_ack_i in the sensitivity list is not used in the process
@N:CD630 : gdp_clut.vhd(22) | Synthesizing work.gdp_clut.rtl 
Post processing for work.gdp_clut.rtl
Post processing for work.gdp_video.rtl
@A:CL282 : gdp_video.vhd(155) | Feedback mux created for signal isCursor -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
Post processing for work.gdp_top.rtl
@N:CD630 : gdp_bi.vhd(22) | Synthesizing work.gdp_bi.rtl 
@N:CD630 : InputSync-e.vhd(15) | Synthesizing work.inputsync.rtl 
Post processing for work.inputsync.rtl
Post processing for work.gdp_bi.rtl
Post processing for work.gdp_lattice_top.rtl
@W:CL252 : gdp_lattice_top.vhd(443) | Bit 0 of signal vdip_data is floating -- simulation mismatch possible.
@W:CL252 : gdp_lattice_top.vhd(443) | Bit 1 of signal vdip_data is floating -- simulation mismatch possible.
@W:CL252 : gdp_lattice_top.vhd(443) | Bit 2 of signal vdip_data is floating -- simulation mismatch possible.
@W:CL252 : gdp_lattice_top.vhd(443) | Bit 3 of signal vdip_data is floating -- simulation mismatch possible.
@W:CL252 : gdp_lattice_top.vhd(443) | Bit 4 of signal vdip_data is floating -- simulation mismatch possible.
@W:CL252 : gdp_lattice_top.vhd(443) | Bit 5 of signal vdip_data is floating -- simulation mismatch possible.
@W:CL252 : gdp_lattice_top.vhd(443) | Bit 6 of signal vdip_data is floating -- simulation mismatch possible.
@W:CL252 : gdp_lattice_top.vhd(443) | Bit 7 of signal vdip_data is floating -- simulation mismatch possible.
@W:CL240 : gdp_lattice_top.vhd(442) | vdip_cs is not assigned a value (floating) -- simulation mismatch possible. 
@W:CL169 : gdp_lattice_top.vhd(458) | Pruning register shreg(9 downto 0)  
@N:CD630 : gdp_intercon.vhd(18) | Synthesizing work.wb_interconnect.intercon 
@N:CD233 : gdp_intercon.vhd(170) | Using sequential encoding for type state_type
@W:CD434 : gdp_intercon.vhd(376) | Signal sys_clk_i in the sensitivity list is not used in the process
@W:CD434 : gdp_intercon.vhd(376) | Signal sys_reset_n_i in the sensitivity list is not used in the process
@W:CD434 : gdp_intercon.vhd(376) | Signal gdphs_sram_cs in the sensitivity list is not used in the process
@W:CD434 : gdp_intercon.vhd(376) | Signal gdphs_wbm_strobe in the sensitivity list is not used in the process
@W:CD434 : gdp_intercon.vhd(376) | Signal gdphs_wbm_cycle in the sensitivity list is not used in the process
@W:CD434 : gdp_intercon.vhd(376) | Signal hsync_i in the sensitivity list is not used in the process
@W:CD434 : gdp_intercon.vhd(376) | Signal vsync_i in the sensitivity list is not used in the process
@W:CG296 : gdp_intercon.vhd(376) | Incomplete sensitivity list - assuming completeness
@W:CG290 : gdp_intercon.vhd(378) | Referenced variable black_i is not in sensitivity list
@W:CD638 : gdp_intercon.vhd(171) | Signal state is undriven 
@W:CD638 : gdp_intercon.vhd(171) | Signal next_state is undriven 
Post processing for work.wb_interconnect.intercon
@W:CL240 : gdp_intercon.vhd(31) | IRQ1_o is not assigned a value (floating) -- simulation mismatch possible. 
@W:CL240 : gdp_intercon.vhd(30) | IRQ0_o is not assigned a value (floating) -- simulation mismatch possible. 
@W:CL111 : gdp_intercon.vhd(207) | All reachable assignments to vdip_cs assign '0'; register removed by optimization
@W:CL117 : gdp_intercon.vhd(473) | Latch generated from process for signal sram_buffer(15 downto 0); possible missing assignment in an if or case statement.
@N:CD630 : nkc16_wb_wrapper.vhd(25) | Synthesizing work.nkc16_wb_wrapper.rtl 
@W:CD434 : nkc16_wb_wrapper.vhd(292) | Signal strobe in the sensitivity list is not used in the process
@W:CG296 : nkc16_wb_wrapper.vhd(292) | Incomplete sensitivity list - assuming completeness
@W:CG290 : nkc16_wb_wrapper.vhd(297) | Referenced variable fpga_en is not in sensitivity list
Post processing for work.nkc16_wb_wrapper.rtl
@W:CL240 : nkc16_wb_wrapper.vhd(61) | debug_o is not assigned a value (floating) -- simulation mismatch possible. 
Post processing for work.gdp_fpgaii_top.rtl
@W:CL159 : gdp_intercon.vhd(63) | Input Hsync_i is unused
@W:CL159 : gdp_intercon.vhd(64) | Input Vsync_i is unused
@N:CL201 : gdp_video.vhd(289) | Trying to extract state machine for register rd_state
Extracted state machine for register rd_state
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
@W:CL247 : gdp_video.vhd(52) | Input port bit 11 of cx1_i(11 downto 0) is unused 
@W:CL247 : gdp_video.vhd(53) | Input port bit 11 of cx2_i(11 downto 0) is unused 
@W:CL247 : gdp_video.vhd(54) | Input port bit 11 of cy1_i(11 downto 0) is unused 
@W:CL247 : gdp_video.vhd(55) | Input port bit 11 of cy2_i(11 downto 0) is unused 
@W:CL157 : gdp_video.vhd(140) | Output monitoring_o has undriven bits -- simulation mismatch possible.
@W:CL159 : gdp_video.vhd(33) | Input rd_ack_i is unused
@N:CL201 : gdp_decoder.vhd(188) | Trying to extract state machine for register drawCmd
Extracted state machine for register drawCmd
State machine has 5 reachable states with original encodings of:
   00001
   00010
   00100
   01000
   10000
@W:CL159 : gdp_decoder.vhd(52) | Input hsync_i is unused
@W:CL159 : gdp_decoder.vhd(61) | Input Rd_i is unused
@N:CL201 : gdp_bresenham.vhd(133) | Trying to extract state machine for register state
Extracted state machine for register state
State machine has 5 reachable states with original encodings of:
   00001
   00010
   00100
   01000
   10000
@N:CL201 : gdp_character.vhd(198) | Trying to extract state machine for register state
Extracted state machine for register state
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
@W:CL159 : gdp_character.vhd(67) | Input rom_data_i is unused
@W:CL159 : gdp_character.vhd(69) | Input rom_busy_i is unused
@N:CL201 : gdp_kernel.vhd(610) | Trying to extract state machine for register state
Extracted state machine for register state
State machine has 5 reachable states with original encodings of:
   00001
   00010
   00100
   01000
   10000
@W:CL159 : gdp_kernel.vhd(54) | Input kernel_ack_i is unused
@N:CL201 : gdp_vram.vhd(197) | Trying to extract state machine for register state
Extracted state machine for register state
State machine has 3 reachable states with original encodings of:
   00
   01
   10
@W:CL159 : gdp_vram.vhd(38) | Input chr_rom_addr_i is unused
@W:CL159 : gdp_vram.vhd(40) | Input chr_rom_ena_i is unused
@W:CL157 : gdp_top.vhd(329) | Output monitoring_o has undriven bits -- simulation mismatch possible.
@N:CL201 : PS2_Decoder.vhd(538) | Trying to extract state machine for register fetch_state
Extracted state machine for register fetch_state
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
@N:CL201 : PS2Keyboard.vhd(563) | Trying to extract state machine for register kbd_init_state
Extracted state machine for register kbd_init_state
State machine has 3 reachable states with original encodings of:
   00
   01
   10
@W:CL246 : PS2Keyboard.vhd(48) | Input port bits 7 to 2 of datain_i(7 downto 0) are unused 
@N:CL201 : PS2_Interface.vhd(167) | Trying to extract state machine for register state
Extracted state machine for register state
State machine has 5 reachable states with original encodings of:
   00001
   00010
   00100
   01000
   10000
@N:CL201 : PS2Mouse.vhd(287) | Trying to extract state machine for register mouse_state
Extracted state machine for register mouse_state
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
@W:CL159 : PS2Mouse.vhd(45) | Input DataIn_i is unused
@W:CL159 : PS2Mouse.vhd(46) | Input Rd_i is unused
@N:CL201 : Ser1.vhd(572) | Trying to extract state machine for register rx_state
Extracted state machine for register rx_state
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
@N:CL201 : Ser1.vhd(425) | Trying to extract state machine for register tx_state
Extracted state machine for register tx_state
State machine has 3 reachable states with original encodings of:
   00
   01
   10
@W:CL159 : gdp_lattice_top.vhd(54) | Input gdphs_wbs_cycle is unused
@W:CL159 : gdp_lattice_top.vhd(70) | Input gdphs_wbm_ack is unused
@N:CL201 : gide.vhd(127) | Trying to extract state machine for register state
Extracted state machine for register state
State machine has 25 reachable states with original encodings of:
   000000000000000000000000000000000001
   000000000000000000000000000000000010
   000000000000000000000000000000000100
   000000000000000000000000000000001000
   000000000000000000000000000000010000
   000000000000000000000000000000100000
   000000000000000000000000000001000000
   000000000000000000000000000010000000
   000000000000000000000000100000000000
   000000000000000000000001000000000000
   000000000000000000000010000000000000
   000000000000000000000100000000000000
   000000000000000000001000000000000000
   000000000000000000010000000000000000
   000000000000000000100000000000000000
   000000000000001000000000000000000000
   000000000000010000000000000000000000
   000000000000100000000000000000000000
   000000000001000000000000000000000000
   000000000100000000000000000000000000
   000000010000000000000000000000000000
   000000100000000000000000000000000000
   000001000000000000000000000000000000
   010000000000000000000000000000000000
   100000000000000000000000000000000000
@W:CL159 : gide.vhd(39) | Input gide_wbs_cycle is unused
@W:CL159 : gide.vhd(48) | Input IDE_INT is unused
@W:CL159 : sram.vhd(22) | Input sram_reset_n is unused
@W:CL159 : sram.vhd(23) | Input sram_clk is unused
@W:CL159 : sram.vhd(31) | Input sram_wbs_cycle is unused
@END
Process took 0h:00m:05s realtime, 0h:00m:05s cputime
# Fri Oct 10 21:51:26 2014

###########################################################]

Premap Report Synopsys Lattice Technology Pre-mapping, Version maplat, Build 437R, Built Jul 16 2012 10:38:54 Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc. Product Version F-2012.03L-1 Mapper Startup Complete (Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB) Linked File: GDP-FPGAII Printing clock summary report in "D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGA2.4.2\GDPFPGAII\GDPFPGAII_scck.rpt" file @N:MF248 : | Running in 64-bit mode. @N:MF257 : | Gated clock conversion enabled @N:MF546 : | Generated clock conversion enabled Design Input Complete (Time elapsed 0h:00m:00s; Memory used current: 96MB peak: 98MB) Mapper Initialization Complete (Time elapsed 0h:00m:00s; Memory used current: 97MB peak: 98MB) Start loading timing files (Time elapsed 0h:00m:00s; Memory used current: 110MB peak: 110MB) Finished loading timing files (Time elapsed 0h:00m:00s; Memory used current: 110MB peak: 113MB) @W:BN287 : gdp_clut.vhd(56) | Register clut_15[8:0] with reset has an initial value of 1. Ignoring initial value. @W:BN287 : gdp_clut.vhd(56) | Register clut_14[8:0] with reset has an initial value of 1. Ignoring initial value. @W:BN287 : gdp_clut.vhd(56) | Register clut_13[8:0] with reset has an initial value of 1. Ignoring initial value. @W:BN287 : gdp_clut.vhd(56) | Register clut_12[8:0] with reset has an initial value of 1. Ignoring initial value. @W:BN287 : gdp_clut.vhd(56) | Register clut_11[8:0] with reset has an initial value of 1. Ignoring initial value. @W:BN287 : gdp_clut.vhd(56) | Register clut_10[8:0] with reset has an initial value of 1. Ignoring initial value. @W:BN287 : gdp_clut.vhd(56) | Register clut_9[8:0] with reset has an initial value of 1. Ignoring initial value. @W:BN287 : gdp_clut.vhd(56) | Register clut_8[8:0] with reset has an initial value of 1. Ignoring initial value. @W:BN287 : gdp_clut.vhd(56) | Register clut_7[8:0] with reset has an initial value of 1. Ignoring initial value. @W:BN287 : gdp_clut.vhd(56) | Register clut_6[8:0] with reset has an initial value of 1. Ignoring initial value. @W:BN287 : gdp_clut.vhd(56) | Register clut_5[8:0] with reset has an initial value of 1. Ignoring initial value. @W:BN287 : gdp_clut.vhd(56) | Register clut_4[8:0] with reset has an initial value of 1. Ignoring initial value. @W:BN287 : gdp_clut.vhd(56) | Register clut_3[8:0] with reset has an initial value of 1. Ignoring initial value. @W:BN287 : gdp_clut.vhd(56) | Register clut_2[8:0] with reset has an initial value of 1. Ignoring initial value. @W:FX474 : | User-specified initial value found in some of the sequential elements. Applying an initial value to a register may not produce optimum synthesis results. For example, registers with initial values may become preserved which would prevent retiming/pipelining from being performed. To improve synthesis results, remove register initialization from the RTL code. @W:MT462 : gdp_intercon.vhd(378) | Net INTERCON.ARBITER\.un1_black_i appears to be an unidentified clock source. Assuming default frequency. Clock Summary ************** Start Requested Requested Clock Clock Clock Frequency Period Type Group --------------------------------------------------------------------------------------------------------------------- System 1.0 MHz 1000.000 system system_clkgroup gdp_fpgaii_top|clk_i 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_0 gide|q_derived_clock[1] 1.0 MHz 1000.000 derived (from gdp_fpgaii_top|clk_i) Autoconstr_clkgroup_0 ===================================================================================================================== @W:MT529 : gdp_intercon.vhd(207) | Found inferred clock gdp_fpgaii_top|clk_i which controls 1348 sequential elements including INTERCON/t1_cs. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. syn_allowed_resources : blockrams=10 set on top level netlist gdp_fpgaii_top Finished Pre Mapping Phase. (Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 137MB) Pre-mapping successful! At Mapper Exit (Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 137MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Fri Oct 10 21:51:27 2014 ###########################################################] Map & Optimize Report Synopsys Lattice Technology Mapper, Version maplat, Build 437R, Built Jul 16 2012 10:38:54 Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc. Product Version F-2012.03L-1 Mapper Startup Complete (Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB) @N:MF248 : | Running in 64-bit mode. @N:MF257 : | Gated clock conversion enabled @N:MF546 : | Generated clock conversion enabled Design Input Complete (Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB) Mapper Initialization Complete (Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB) Start loading timing files (Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 105MB) Finished loading timing files (Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 107MB) Starting Optimization and Mapping (Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 137MB) @W:MO111 : gdp_video.vhd(140) | Tristate driver monitoring_o_1 on net monitoring_o_1 has its enable tied to GND (module gdp_video) @W:MO111 : gdp_video.vhd(140) | Tristate driver monitoring_o_2 on net monitoring_o_2 has its enable tied to GND (module gdp_video) @W:MO111 : gdp_video.vhd(140) | Tristate driver monitoring_o_3 on net monitoring_o_3 has its enable tied to GND (module gdp_video) @W:MO111 : gdp_video.vhd(140) | Tristate driver monitoring_o_4 on net monitoring_o_4 has its enable tied to GND (module gdp_video) @W:MO111 : gdp_video.vhd(140) | Tristate driver monitoring_o_5 on net monitoring_o_5 has its enable tied to GND (module gdp_video) @W:MO111 : gdp_video.vhd(140) | Tristate driver monitoring_o_6 on net monitoring_o_6 has its enable tied to GND (module gdp_video) @W:MO111 : gdp_video.vhd(140) | Tristate driver monitoring_o_7 on net monitoring_o_7 has its enable tied to GND (module gdp_video) @W:MO111 : gdp_top.vhd(329) | Tristate driver monitoring_o_1 on net monitoring_o_1 has its enable tied to GND (module gdp_top) @W:MO111 : gdp_top.vhd(329) | Tristate driver monitoring_o_2 on net monitoring_o_2 has its enable tied to GND (module gdp_top) @W:MO111 : gdp_top.vhd(329) | Tristate driver monitoring_o_3 on net monitoring_o_3 has its enable tied to GND (module gdp_top) @W:MO111 : gdp_top.vhd(329) | Tristate driver monitoring_o_4 on net monitoring_o_4 has its enable tied to GND (module gdp_top) @W:MO111 : gdp_top.vhd(329) | Tristate driver monitoring_o_5 on net monitoring_o_5 has its enable tied to GND (module gdp_top) @W:MO111 : gdp_top.vhd(329) | Tristate driver monitoring_o_6 on net monitoring_o_6 has its enable tied to GND (module gdp_top) @W:MO111 : gdp_top.vhd(329) | Tristate driver monitoring_o_7 on net monitoring_o_7 has its enable tied to GND (module gdp_top) @W:MO111 : gdp_top.vhd(329) | Tristate driver monitoring_o_8 on net monitoring_o_8 has its enable tied to GND (module gdp_top) @W:MO111 : gdp_top.vhd(329) | Tristate driver monitoring_o_9 on net monitoring_o_9 has its enable tied to GND (module gdp_top) @W:MO111 : gdp_top.vhd(329) | Tristate driver monitoring_o_10 on net monitoring_o_10 has its enable tied to GND (module gdp_top) @W:MO111 : gdp_top.vhd(329) | Tristate driver monitoring_o_11 on net monitoring_o_11 has its enable tied to GND (module gdp_top) @W:MO111 : gdp_top.vhd(329) | Tristate driver monitoring_o_12 on net monitoring_o_12 has its enable tied to GND (module gdp_top) @W:MO111 : gdp_top.vhd(329) | Tristate driver monitoring_o_13 on net monitoring_o_13 has its enable tied to GND (module gdp_top) @W:MO111 : gdp_top.vhd(329) | Tristate driver monitoring_o_14 on net monitoring_o_14 has its enable tied to GND (module gdp_top) @W:MO111 : gdp_top.vhd(329) | Tristate driver monitoring_o_15 on net monitoring_o_15 has its enable tied to GND (module gdp_top) @W:MO111 : ps2keyboard.vhd(55) | Tristate driver monitoring_o_1 on net monitoring_o_1 has its enable tied to GND (module PS2Keyboard) @W:MO111 : ps2keyboard.vhd(55) | Tristate driver monitoring_o_2 on net monitoring_o_2 has its enable tied to GND (module PS2Keyboard) @W:MO111 : ps2keyboard.vhd(55) | Tristate driver monitoring_o_3 on net monitoring_o_3 has its enable tied to GND (module PS2Keyboard) @W:MO111 : ps2keyboard.vhd(55) | Tristate driver monitoring_o_4 on net monitoring_o_4 has its enable tied to GND (module PS2Keyboard) @W:MO111 : ps2keyboard.vhd(55) | Tristate driver monitoring_o_5 on net monitoring_o_5 has its enable tied to GND (module PS2Keyboard) @W:MO111 : ps2keyboard.vhd(55) | Tristate driver monitoring_o_6 on net monitoring_o_6 has its enable tied to GND (module PS2Keyboard) @N:BN362 : wf2149ip_top_soc.vhd(123) | Removing sequential instance impl_sound\.Sound_inst.PORT_B[7:0] of view:PrimLib.dffre(prim) in hierarchy view:work.gdp_lattice_top(rtl) because there are no references to its outputs @N:BN362 : wf2149ip_top_soc.vhd(123) | Removing sequential instance impl_sound\.Sound_inst.PORT_A[7:0] of view:PrimLib.dffre(prim) in hierarchy view:work.gdp_lattice_top(rtl) because there are no references to its outputs @N:BN362 : wf2149ip_top_soc.vhd(67) | Removing sequential instance impl_sound\.Sound_inst.P_WAVSTRB\.tmp of view:PrimLib.dffre(prim) in hierarchy view:work.gdp_lattice_top(rtl) because there are no references to its outputs Available hyper_sources - for debug and ip models None Found @N:FX493 : | Applying initial value "111111111" on instance GDPHS.GDP.video.use_clut.clut_inst.clut_1[8:0] @N:FX493 : | Applying initial value "000000000" on instance GDPHS.GDP.video.use_clut.clut_inst.clut_0[8:0] @N:FX493 : | Applying initial value "00" on instance GDPHS.sync_reset.reset_sync.sync_reset®reset_sync®tmp_v[1:0] @N:FX493 : | Applying initial value "00000000" on instance GDPHS.GDP.color_reg[7:0] @W:MT462 : gdp_intercon.vhd(378) | Net INTERCON.ARBITER\.un1_black_i appears to be an unidentified clock source. Assuming default frequency. @N:MT206 : | Auto Constrain mode is enabled @N:FA239 : gdp_kernel.vhd(390) | ROM cdx[6:0] mapped in logic. @N:FA239 : gdp_kernel.vhd(390) | ROM cdx[6:0] mapped in logic. @N:MO106 : gdp_kernel.vhd(390) | Found ROM, 'cdx[6:0]', 15 words by 7 bits @N:FA239 : ser1.vhd(282) | ROM un10_baud_cnt[10:0] mapped in logic. @N:FA239 : ser1.vhd(282) | ROM un10_baud_cnt[10:0] mapped in logic. @N:MO106 : ser1.vhd(282) | Found ROM, 'un10_baud_cnt[10:0]', 16 words by 11 bits @N:FA239 : wf2149ip_wave.vhd(461) | ROM VOLUME_C[7:0] mapped in logic. @N:FA239 : wf2149ip_wave.vhd(427) | ROM VOLUME_B[7:0] mapped in logic. @N:FA239 : wf2149ip_wave.vhd(393) | ROM VOLUME_A[7:0] mapped in logic. @N:FA239 : wf2149ip_wave.vhd(461) | ROM VOLUME_C[7:0] mapped in logic. @N:MO106 : wf2149ip_wave.vhd(461) | Found ROM, 'VOLUME_C[7:0]', 31 words by 8 bits @N:FA239 : wf2149ip_wave.vhd(427) | ROM VOLUME_B[7:0] mapped in logic. @N:MO106 : wf2149ip_wave.vhd(427) | Found ROM, 'VOLUME_B[7:0]', 31 words by 8 bits @N:FA239 : wf2149ip_wave.vhd(393) | ROM VOLUME_A[7:0] mapped in logic. @N:MO106 : wf2149ip_wave.vhd(393) | Found ROM, 'VOLUME_A[7:0]', 31 words by 8 bits Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) @N: : gdp_top.vhd(375) | Found counter in view:work.gdp_lattice_top(rtl) inst GDP.clut_addr[3:0] Encoding state machine rd_state[0:3] (netlist:statemachine) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 Encoding state machine state[0:4] (netlist:statemachine) original code -> new code 00001 -> 00001 00010 -> 00010 00100 -> 00100 01000 -> 01000 10000 -> 10000 @N:FX404 : gdp_kernel.vhd(491) | Found addmux in view:work.gdp_kernel(rtl) inst kernel_addr_o[15:0] from un1_cached_kernel_addr_1[15:0] Encoding state machine drawCmd[0:4] (netlist:statemachine) original code -> new code 00001 -> 00001 00010 -> 00010 00100 -> 00100 01000 -> 01000 10000 -> 10000 Encoding state machine state[0:4] (netlist:statemachine) original code -> new code 00001 -> 00001 00010 -> 00010 00100 -> 00100 01000 -> 01000 10000 -> 10000 @N: : gdp_bresenham.vhd(133) | Found updn counter in view:work.gdp_bresenham(rtl) inst posx[11:0] @N: : gdp_bresenham.vhd(133) | Found updn counter in view:work.gdp_bresenham(rtl) inst posy[11:0] @N: : gdp_bresenham.vhd(133) | Found counter in view:work.gdp_bresenham(rtl) inst linestyle_count[3:0] @N:FX404 : numeric.vhd(903) | Found addmux in view:work.gdp_bresenham(rtl) inst fsm_comb\.resize\.inf_abs1[9:0] from inf_abs1_a_1[10:1] @N:FX404 : numeric.vhd(903) | Found addmux in view:work.gdp_bresenham(rtl) inst fsm_comb\.resize\.inf_abs0[9:0] from inf_abs0_a_0[10:1] @N:MF179 : | Found 12 bit by 12 bit '==' comparator, 'fsm_comb\.un4_enable_i' @N:MF179 : | Found 12 bit by 12 bit '==' comparator, 'fsm_comb\.un8_enable_i' @N:MF179 : | Found 12 bit by 12 bit '==' comparator, 'fsm_comb\.un10_ack_expected' @N:MF179 : | Found 12 bit by 12 bit '==' comparator, 'fsm_comb\.un16_ack_expected' Encoding state machine state[0:3] (netlist:statemachine) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:FX702 : gdp_font_ram.vhd(23) | Found startup values on RAM instance use_int_rom®char_rom.iram[7:0] @N:FX276 : gdp_font_ram.vhd(23) | Startup value iram_0_0.INITVAL_00 = 092360C46401013046120547F054240141F0141F014000060000600000000BE00000000000000000 @N:FX276 : gdp_font_ram.vhd(23) | Startup value iram_0_0.INITVAL_01 = 0E0B0000000100807C080102A0387F0382A0001C0444100000082220380000007016000005004455 @N:FX276 : gdp_font_ram.vhd(23) | Startup value iram_0_0.INITVAL_02 = 08246092490A262000000FE020000007C410823E004040101004000000600C000010080100801000 @N:FX276 : gdp_font_ram.vhd(23) | Startup value iram_0_0.INITVAL_03 = 0924900C36092490923600605012110C230092490943C0724508A4508E080FE080100F0664D09241 @N:FX276 : gdp_font_ram.vhd(23) | Startup value iram_0_0.INITVAL_04 = 00C090A2010040802822082000281402814028000822202808000000ECB6000000003606C0003C29 @N:FX276 : gdp_font_ram.vhd(23) | Startup value iram_0_0.INITVAL_05 = 0127F08249092490FE3E082410827F044410824107C36092490927F0FC09012090FC5E0AA5D0823E @N:FX276 : gdp_font_ram.vhd(23) | Startup value iram_0_0.INITVAL_06 = 080400807F08222028080FE3F0804008020000410FE410007F010080107F0F4490924107C0101209 @N:FX276 : gdp_font_ram.vhd(23) | Startup value iram_0_0.INITVAL_07 = 04C46052190127F0BC210A24107C06012090127F07C410824107C7F010040047F0FE02018020FE40 @N:FX276 : gdp_font_ram.vhd(23) | Startup value iram_0_0.INITVAL_08 = 0E00800E6302808028630FE20030200FE1F040400401F07E400804007E010027F002010644909249 @N:FX276 : gdp_font_ram.vhd(23) | Startup value iram_0_0.INITVAL_09 = 10080100801000400401004040007F08241000200200800802000410827F0004308A490A26100E08 @N:FX276 : gdp_font_ram.vhd(23) | Startup value iram_0_0.INITVAL_0A = 01000090540A838000400FE440883809044088380003C088440FE40080780A8540E0000000B00E00 @N:FX276 : gdp_font_ram.vhd(23) | Startup value iram_0_0.INITVAL_0B = 0807E00400088280207E000000E88008000000000F40000078008040FE000F8A414898000020147C @N:FX276 : gdp_font_ram.vhd(23) | Startup value iram_0_0.INITVAL_0C = 00004008080F800100FC0482403018048241F800070440883800078008040F8000F0040F8040F800 @N:FX276 : gdp_font_ram.vhd(23) | Startup value iram_0_0.INITVAL_0D = 0401C00044090380484407840060400780C060400600C0807C08040078200883E00800048540A848 @N:FX276 : gdp_font_ram.vhd(23) | Startup value iram_0_0.INITVAL_0E = 0AA2A0AA2A0AA04010040040401036082410000000077000000824106C0800004098540C8401F8A0 @N:FX276 : gdp_font_ram.vhd(23) | Startup value iram_0_0.INITVAL_0F = 0000000000000000000000000000000000000000000000000000000000F01E0F01E0FF1FEFF1FEFF @N:FX276 : gdp_font_ram.vhd(23) | Startup value iram_0_0.INITVAL_10 = 092360C46401013046120547F054240141F0141F014000060000600000000BE00000000000000000 @N:FX276 : gdp_font_ram.vhd(23) | Startup value iram_0_0.INITVAL_11 = 0E0B0000000100807C080102A0387F0382A0001C0444100000082220380000007016000005004455 @N:FX276 : gdp_font_ram.vhd(23) | Startup value iram_0_0.INITVAL_12 = 08246092490A262000000FE020000007C410823E004040101004000000600C000010080100801000 @N:FX276 : gdp_font_ram.vhd(23) | Startup value iram_0_0.INITVAL_13 = 0924900C36092490923600605012110C230092490943C0724508A4508E080FE080100F0664D09241 @N:FX276 : gdp_font_ram.vhd(23) | Startup value iram_0_0.INITVAL_14 = 00C090A2010040802822082000281402814028000822202808000000ECB6000000003606C0003C29 @N:FX276 : gdp_font_ram.vhd(23) | Startup value iram_0_0.INITVAL_15 = 0127F08249092490FE3E082410827F044410824107C36092490927F0FC09012090FC5E0AA5D0823E @N:FX276 : gdp_font_ram.vhd(23) | Startup value iram_0_0.INITVAL_16 = 080400807F08222028080FE3F0804008020000410FE410007F010080107F0F4490924107C0101209 @N:FX276 : gdp_font_ram.vhd(23) | Startup value iram_0_0.INITVAL_17 = 04C46052190127F0BC210A24107C06012090127F07C410824107C7F010040047F0FE02018020FE40 @N:FX276 : gdp_font_ram.vhd(23) | Startup value iram_0_0.INITVAL_18 = 0E00800E6302808028630FE20030200FE1F040400401F07E400804007E010027F002010644909249 @N:FX276 : gdp_font_ram.vhd(23) | Startup value iram_0_0.INITVAL_19 = 10080100801000400401004040FA40080400FA3D084420843D0FA0A0120A0FA4308A490A26100E08 @N:FX276 : gdp_font_ram.vhd(23) | Startup value iram_0_0.INITVAL_1A = 01000090540A838000400FE440883809044088380003C088440FE40080780A8540E0000000B00E00 @N:FX276 : gdp_font_ram.vhd(23) | Startup value iram_0_0.INITVAL_1B = 0807E00400088280207E000000E88008000000000F40000078008040FE000F8A414898000020147C @N:FX276 : gdp_font_ram.vhd(23) | Startup value iram_0_0.INITVAL_1C = 00004008080F800100FC0482403018048241F800070440883800078008040F8000F0040F8040F800 @N:FX276 : gdp_font_ram.vhd(23) | Startup value iram_0_0.INITVAL_1D = 0401C00044090380484407840060400780C060400600C0807C08040078200883E00800048540A848 @N:FX276 : gdp_font_ram.vhd(23) | Startup value iram_0_0.INITVAL_1E = 0AA2A0AA2A0AA3209A010FE000807D0804007A390884407200082780A8540E204098540C8401F8A0 @N:FX276 : gdp_font_ram.vhd(23) | Startup value iram_0_0.INITVAL_1F = 0000007008010080103801008010080700801008010380100801008000F01E0F01E0FF1FEFF1FEFF @N:FX702 : gdp_font_ram.vhd(23) | Found startup values on RAM instance use_int_rom®char_rom.iram[7:0] @N: : gdp_character.vhd(198) | Found updn counter in view:work.gdp_character(rtl) inst posx[11:0] @N: : gdp_character.vhd(198) | Found counter in view:work.gdp_character(rtl) inst posy[11:0] @N: : gdp_character.vhd(198) | Found counter in view:work.gdp_character(rtl) inst xscnt[3:0] @N: : gdp_character.vhd(198) | Found counter in view:work.gdp_character(rtl) inst ypcnt[3:0] @N: : gdp_character.vhd(198) | Found counter in view:work.gdp_character(rtl) inst yscnt[3:0] Encoding state machine state[0:2] (netlist:statemachine) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine tx_state[0:2] (netlist:statemachine) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine rx_state[0:3] (netlist:statemachine) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:FX404 : wf2149ip_wave.vhd(200) | Found addmux in view:work.WF2149IP_WAVE(behavior) inst NOISEGENERATOR\.cnt_noise_6[4:0] from un1_cnt_noise_2[4:0] @N:FX404 : wf2149ip_wave.vhd(144) | Found addmux in view:work.WF2149IP_WAVE(behavior) inst MUSICGENERATOR\.cnt_ch_a_6[11:0] from un1_cnt_ch_a_2[11:0] @N:FX404 : wf2149ip_wave.vhd(144) | Found addmux in view:work.WF2149IP_WAVE(behavior) inst MUSICGENERATOR\.cnt_ch_b_5[11:0] from un1_cnt_ch_b_2[11:0] @N:FX404 : wf2149ip_wave.vhd(144) | Found addmux in view:work.WF2149IP_WAVE(behavior) inst MUSICGENERATOR\.cnt_ch_c_5[11:0] from un1_cnt_ch_c_2[11:0] @N: : timer.vhd(77) | Found counter in view:work.Timer(rtl) inst Timer_reg[15:0] @N: : timer.vhd(77) | Found counter in view:work.Timer(rtl) inst prescaler[5:0] Encoding state machine kbd_init_state[0:2] (netlist:statemachine) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine fetch_state[0:3] (netlist:statemachine) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:FX404 : ps2_decoder.vhd(322) | Found addmux in view:work.PS2_Decoder(rtl) inst next_LookupAddress_23[8:0] from un1_nkccode_v_2[8:0] Encoding state machine state[0:4] (netlist:statemachine) original code -> new code 00001 -> 00001 00010 -> 00010 00100 -> 00100 01000 -> 01000 10000 -> 10000 @N: : ps2_interface.vhd(167) | Found counter in view:work.PS2_Interface_PS2if(rtl) inst q[3:0] @N: : ps2_interface.vhd(167) | Found counter in view:work.PS2_Interface_PS2if(rtl) inst delayCnt[11:0] @W:BN132 : ps2_interface.vhd(167) | Removing instance GDPHS.impl_key2.kbd.PS2if.CmdReg[7], because it is equivalent to instance GDPHS.impl_key2.kbd.PS2if.CmdReg[6] @W:BN132 : ps2_interface.vhd(167) | Removing instance GDPHS.impl_key2.kbd.PS2if.CmdReg[6], because it is equivalent to instance GDPHS.impl_key2.kbd.PS2if.CmdReg[5] Encoding state machine mouse_state[0:3] (netlist:statemachine) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 Encoding state machine state[0:4] (netlist:statemachine) original code -> new code 00001 -> 00001 00010 -> 00010 00100 -> 00100 01000 -> 01000 10000 -> 10000 @N: : ps2_interface.vhd(167) | Found counter in view:work.PS2_Interface(rtl) inst q[3:0] @N: : ps2_interface.vhd(167) | Found counter in view:work.PS2_Interface(rtl) inst delayCnt[11:0] @W:BN132 : ps2_interface.vhd(167) | Removing instance GDPHS.impl_mouse.mouse.PS2if.CmdReg[7], because it is equivalent to instance GDPHS.impl_mouse.mouse.PS2if.CmdReg[6] Encoding state machine state[0:24] (netlist:statemachine) original code -> new code 000000000000000000000000000000000001 -> 0000000000000000000000001 000000000000000000000000000000000010 -> 0000000000000000000000010 000000000000000000000000000000000100 -> 0000000000000000000000100 000000000000000000000000000000001000 -> 0000000000000000000001000 000000000000000000000000000000010000 -> 0000000000000000000010000 000000000000000000000000000000100000 -> 0000000000000000000100000 000000000000000000000000000001000000 -> 0000000000000000001000000 000000000000000000000000000010000000 -> 0000000000000000010000000 000000000000000000000000100000000000 -> 0000000000000000100000000 000000000000000000000001000000000000 -> 0000000000000001000000000 000000000000000000000010000000000000 -> 0000000000000010000000000 000000000000000000000100000000000000 -> 0000000000000100000000000 000000000000000000001000000000000000 -> 0000000000001000000000000 000000000000000000010000000000000000 -> 0000000000010000000000000 000000000000000000100000000000000000 -> 0000000000100000000000000 000000000000001000000000000000000000 -> 0000000001000000000000000 000000000000010000000000000000000000 -> 0000000010000000000000000 000000000000100000000000000000000000 -> 0000000100000000000000000 000000000001000000000000000000000000 -> 0000001000000000000000000 000000000100000000000000000000000000 -> 0000010000000000000000000 000000010000000000000000000000000000 -> 0000100000000000000000000 000000100000000000000000000000000000 -> 0001000000000000000000000 000001000000000000000000000000000000 -> 0010000000000000000000000 010000000000000000000000000000000000 -> 0100000000000000000000000 100000000000000000000000000000000000 -> 1000000000000000000000000 @N:BN362 : gdp_global-p.vhd(57) | Removing sequential instance dec.drawCmd[4] in hierarchy view:work.gdp_kernel(rtl) because there are no references to its outputs @W:BN132 : gdp_vram.vhd(197) | Removing instance GDPHS.GDP.vram.rd_pend, because it is equivalent to instance GDPHS.GDP.vram.state[1] @N:BN362 : ps2_interface.vhd(167) | Removing sequential instance impl_mouse\.mouse.PS2if.ParityError in hierarchy view:work.gdp_lattice_top(rtl) because there are no references to its outputs @N:BN362 : ps2_interface.vhd(167) | Removing sequential instance impl_mouse\.mouse.PS2if.ackReceived in hierarchy view:work.gdp_lattice_top(rtl) because there are no references to its outputs @N:BN362 : ps2_interface.vhd(167) | Removing sequential instance impl_key2\.kbd.PS2if.ParityError in hierarchy view:work.gdp_lattice_top(rtl) because there are no references to its outputs @N:BN362 : ps2_interface.vhd(167) | Removing sequential instance impl_key2\.kbd.PS2if.ackReceived in hierarchy view:work.gdp_lattice_top(rtl) because there are no references to its outputs @N:BN362 : ser1.vhd(425) | Removing sequential instance impl_ser1\.ser.tx_irq in hierarchy view:work.gdp_lattice_top(rtl) because there are no references to its outputs @N:BN362 : gdp_vram.vhd(197) | Removing sequential instance GDP.vram.rd_ack_o in hierarchy view:work.gdp_lattice_top(rtl) because there are no references to its outputs Finished factoring (Time elapsed 0h:00m:03s; Memory used current: 171MB peak: 172MB) @N:BN362 : gdp_vram.vhd(197) | Removing sequential instance GDPHS.GDP.vram.kernel_ack_o in hierarchy view:work.gdp_fpgaii_top(rtl) because there are no references to its outputs @N:BN362 : gide.vhd(127) | Removing sequential instance GIDE1.D_WR_EN in hierarchy view:work.gdp_fpgaii_top(rtl) because there are no references to its outputs #################### START OF GENERATED CLOCK OPTIMIZATION REPORT ####################[ ====================================================================================== Instance:Pin Generated Clock Optimization Status ====================================================================================== GIDE1.state[14]:C Done GIDE1.state[15]:C Done GIDE1.state[16]:C Done GIDE1.state[17]:C Done GIDE1.state[18]:C Done GIDE1.state[19]:C Done GIDE1.state[20]:C Done GIDE1.state[21]:C Done GIDE1.state[22]:C Done GIDE1.state[23]:C Done GIDE1.state[24]:C Done GIDE1.state[0]:C Done GIDE1.state[1]:C Done GIDE1.state[2]:C Done GIDE1.state[3]:C Done GIDE1.state[4]:C Done GIDE1.state[5]:C Done GIDE1.state[6]:C Done GIDE1.state[7]:C Done GIDE1.state[8]:C Done GIDE1.state[9]:C Done GIDE1.state[10]:C Done GIDE1.state[11]:C Done GIDE1.state[12]:C Done GIDE1.state[13]:C Done GIDE1.D_WR_LOW_HIGH:C Done GIDE1.IDE_WR_EN:C Done GIDE1.IDE_WR_SIG:C Done GIDE1.TOGGLE:C Done GIDE1.IDE_RD_SIG:C Done GIDE1.CS_BUFFER[1]:C Done GIDE1.CS_BUFFER[0]:C Done GIDE1.ADR_BUFFER[2]:C Done GIDE1.ADR_BUFFER[1]:C Done GIDE1.ADR_BUFFER[0]:C Done GIDE1.DATA_IDE_D[15]:C Done GIDE1.DATA_IDE_D[14]:C Done GIDE1.DATA_IDE_D[13]:C Done GIDE1.DATA_IDE_D[12]:C Done GIDE1.DATA_IDE_D[11]:C Done GIDE1.DATA_IDE_D[10]:C Done GIDE1.DATA_IDE_D[9]:C Done GIDE1.DATA_IDE_D[8]:C Done GIDE1.DATA_IDE_D[7]:C Done GIDE1.DATA_IDE_D[6]:C Done GIDE1.DATA_IDE_D[5]:C Done GIDE1.DATA_IDE_D[4]:C Done GIDE1.DATA_IDE_D[3]:C Done GIDE1.DATA_IDE_D[2]:C Done GIDE1.DATA_IDE_D[1]:C Done GIDE1.DATA_IDE_D[0]:C Done GIDE1.gide_wbs_ack:C Done GIDE1.DATA_D_IDE[15]:C Done GIDE1.DATA_D_IDE[14]:C Done GIDE1.DATA_D_IDE[13]:C Done GIDE1.DATA_D_IDE[12]:C Done GIDE1.DATA_D_IDE[11]:C Done GIDE1.DATA_D_IDE[10]:C Done GIDE1.DATA_D_IDE[9]:C Done GIDE1.DATA_D_IDE[8]:C Done GIDE1.DATA_D_IDE[7]:C Done GIDE1.DATA_D_IDE[6]:C Done GIDE1.DATA_D_IDE[5]:C Done GIDE1.DATA_D_IDE[4]:C Done GIDE1.DATA_D_IDE[3]:C Done GIDE1.DATA_D_IDE[2]:C Done GIDE1.DATA_D_IDE[1]:C Done GIDE1.DATA_D_IDE[0]:C Done ##################### END OF GENERATED CLOCK OPTIMIZATION REPORT #####################] Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:03s; Memory used current: 165MB peak: 175MB) Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:04s; Memory used current: 159MB peak: 175MB) @N:FX211 : | Packed ROM GDPHS.impl_key2\.kbd.PS2dec.p_lookup\.LookupData_1_0[7:0] (9 input, 8 output) to Block SelectRAM @N:FA113 : ps2mouse.vhd(407) | Pipelining module nkc_mouse\.up_v_5[7:0] @N:MF169 : ps2mouse.vhd(383) | Register up_cnt[7:0] pushed in. @N:MF169 : ps2mouse.vhd(383) | Register up_reg[7:0] pushed in. @N:FA113 : ps2mouse.vhd(407) | Pipelining module nkc_mouse\.right_v_5[7:0] @N:MF169 : ps2mouse.vhd(383) | Register right_cnt[7:0] pushed in. @N:MF169 : ps2mouse.vhd(383) | Register right_reg[7:0] pushed in. @N:FA113 : ps2mouse.vhd(407) | Pipelining module nkc_mouse\.left_v_5[7:0] @N:MF169 : ps2mouse.vhd(383) | Register left_cnt[7:0] pushed in. @N:MF169 : ps2mouse.vhd(383) | Register left_reg[7:0] pushed in. @N:FA113 : ps2mouse.vhd(407) | Pipelining module nkc_mouse\.down_v_5[7:0] @N:MF169 : ps2mouse.vhd(383) | Register down_cnt[7:0] pushed in. @N:MF169 : ps2mouse.vhd(383) | Register down_reg[7:0] pushed in. @N:FA113 : dac.vhd(59) | Pipelining module sigmaadder_s[9:0] @N:MF169 : dac.vhd(63) | Register SigmaLatch_q[9:0] pushed in. @N:MF169 : wf2149ip_wave.vhd(502) | Register SUM_VOL[7:0] pushed in. @N:MF169 : wf2149ip_wave.vhd(76) | Register LEVEL_A[4:0] pushed in. @N:MF169 : wf2149ip_wave.vhd(278) | Register VOL_ENV[4:0] pushed in. @N:MF169 : wf2149ip_wave.vhd(76) | Register LEVEL_C[4:0] pushed in. @N:MF169 : wf2149ip_wave.vhd(278) | Register env_up_dnn pushed in. @N:MF169 : wf2149ip_wave.vhd(76) | Register ENV_SHAPE[3:0] pushed in. @N:MF169 : wf2149ip_wave.vhd(76) | Register ENV_RESET pushed in. @N:MF169 : wf2149ip_wave.vhd(278) | Register env_stop pushed in. @N:FA113 : gdp_bresenham.vhd(154) | Pipelining module un1_e_1[10:0] @N:MF169 : gdp_bresenham.vhd(133) | Register e[10:0] pushed in. @N:FA113 : wf2149ip_wave.vhd(504) | Pipelining module un14_sum_v[9:0] @N:MF169 : | Register NoName pushed in. @N:FX404 : gdp_video.vhd(378) | Found addmux in view:work.gdp_fpgaii_top(rtl) inst GDPHS.GDP.vram.ram_address_5_i_m3[15:9] from GDPHS.GDP.video.un3_rd_addr_o[15:9] Starting Early Timing Optimization (Time elapsed 0h:00m:09s; Memory used current: 161MB peak: 175MB) Finished Early Timing Optimization (Time elapsed 0h:00m:15s; Memory used current: 174MB peak: 175MB) Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:15s; Memory used current: 173MB peak: 175MB) Finished preparing to map (Time elapsed 0h:00m:17s; Memory used current: 171MB peak: 175MB) Finished technology mapping (Time elapsed 0h:00m:21s; Memory used current: 225MB peak: 230MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:21s -4.51ns 2616 / 1443 2 0h:00m:21s -4.51ns 2616 / 1443 ------------------------------------------------------------ Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:26s -3.79ns 2622 / 1429 2 0h:00m:26s -3.79ns 2622 / 1429 3 0h:00m:26s -3.79ns 2622 / 1429 4 0h:00m:26s -3.79ns 2622 / 1429 ------------------------------------------------------------ Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:27s -3.67ns 2623 / 1429 2 0h:00m:27s -3.67ns 2623 / 1429 3 0h:00m:27s -3.67ns 2623 / 1429 4 0h:00m:27s -3.67ns 2623 / 1429 ------------------------------------------------------------ @N:FX103 : gdp_bi.vhd(93) | Instance "GDPHS.bi_inst.addr_o[0]" with "109" loads has been replicated "1" time(s) due to a soft fanout limit of "100" Net buffering Report for view:work.gdp_fpgaii_top(rtl): Added 0 Buffers Added 1 Registers via replication Added 0 LUTs via replication Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:28s; Memory used current: 175MB peak: 230MB) @N:FX164 : | The option to pack flops in the IOB has not been specified Finished restoring hierarchy (Time elapsed 0h:00m:30s; Memory used current: 180MB peak: 230MB) Writing Analyst data base D:\Projects\NDR\NDR2.0\EAGLE\GDP-FPGAII 1.x\Software\GDP_FPGA2.4.2\GDPFPGAII\GDPFPGAII.srm Finished Writing Netlist Databases (Time elapsed 0h:00m:31s; Memory used current: 179MB peak: 230MB) Writing EDIF Netlist and constraint files F-2012.03L-1 @N:BW106 : | Synplicity Constraint File capacitance units using default value of 1pF Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:31s; Memory used current: 187MB peak: 230MB) Starting Writing Gated Clock Conversion Report (Time elapsed 0h:00m:32s; Memory used current: 178MB peak: 230MB) ================= Gated clock report ================= The following instances have NOT been converted Seq Inst Instance Port Clock Reason for not converting ------------------------------------------------------------------------------------------------------------------------------------------------------------ INTERCON_sram_bufferio[15] SCLK INTERCON.un1_black_i Gated clock does not have declared clock, add/enable clock constraint in SDC file. INTERCON_sram_bufferio[14] SCLK INTERCON.un1_black_i Gated clock does not have declared clock, add/enable clock constraint in SDC file. INTERCON_sram_bufferio[13] SCLK INTERCON.un1_black_i Gated clock does not have declared clock, add/enable clock constraint in SDC file. INTERCON_sram_bufferio[12] SCLK INTERCON.un1_black_i Gated clock does not have declared clock, add/enable clock constraint in SDC file. INTERCON_sram_bufferio[11] SCLK INTERCON.un1_black_i Gated clock does not have declared clock, add/enable clock constraint in SDC file. INTERCON_sram_bufferio[10] SCLK INTERCON.un1_black_i Gated clock does not have declared clock, add/enable clock constraint in SDC file. INTERCON_sram_bufferio[9] SCLK INTERCON.un1_black_i Gated clock does not have declared clock, add/enable clock constraint in SDC file. INTERCON_sram_bufferio[8] SCLK INTERCON.un1_black_i Gated clock does not have declared clock, add/enable clock constraint in SDC file. INTERCON_sram_bufferio[7] SCLK INTERCON.un1_black_i Gated clock does not have declared clock, add/enable clock constraint in SDC file. INTERCON_sram_bufferio[6] SCLK INTERCON.un1_black_i Gated clock does not have declared clock, add/enable clock constraint in SDC file. INTERCON_sram_bufferio[5] SCLK INTERCON.un1_black_i Gated clock does not have declared clock, add/enable clock constraint in SDC file. INTERCON_sram_bufferio[4] SCLK INTERCON.un1_black_i Gated clock does not have declared clock, add/enable clock constraint in SDC file. INTERCON_sram_bufferio[3] SCLK INTERCON.un1_black_i Gated clock does not have declared clock, add/enable clock constraint in SDC file. INTERCON_sram_bufferio[2] SCLK INTERCON.un1_black_i Gated clock does not have declared clock, add/enable clock constraint in SDC file. INTERCON_sram_bufferio[1] SCLK INTERCON.un1_black_i Gated clock does not have declared clock, add/enable clock constraint in SDC file. INTERCON_sram_bufferio[0] SCLK INTERCON.un1_black_i Gated clock does not have declared clock, add/enable clock constraint in SDC file. ============================================================================================================================================================ ================= End gated clock report ================= Finished Writing Gated Clock Conversion Report (Time elapsed 0h:00m:32s; Memory used current: 178MB peak: 230MB) Starting Writing Generated Clock Conversion Report (Time elapsed 0h:00m:32s; Memory used current: 178MB peak: 230MB) @N:MF333 : | Generated clock conversion enabled, but no generated clocks found in design Finished Writing Generated Clock Conversion Report (Time elapsed 0h:00m:32s; Memory used current: 178MB peak: 230MB) @W:MT246 : ps2_fifo.vhd(297) | Blackbox AGEB2 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : ps2_fifo.vhd(284) | Blackbox ALEB2 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT420 : | Found inferred clock gdp_fpgaii_top|clk_i with period 11.11ns. Please declare a user-defined clock on object "p:clk_i" ##### START OF TIMING REPORT #####[ # Timing Report written on Fri Oct 10 21:52:00 2014 # Top view: gdp_fpgaii_top Requested Frequency: 90.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N:MT320 : | Timing report estimates place and route data. Please look at the place and route timing report for final timing. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock. Performance Summary ******************* Worst slack in design: -1.961 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group -------------------------------------------------------------------------------------------------------------------------------- gdp_fpgaii_top|clk_i 90.0 MHz 76.5 MHz 11.112 13.073 -1.961 inferred Autoconstr_clkgroup_0 System 1996.4 MHz 1696.9 MHz 0.501 0.589 -0.088 system system_clkgroup ================================================================================================================================ Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ----------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ----------------------------------------------------------------------------------------------------------------------------------- System System | 0.501 -0.088 | No paths - | No paths - | No paths - System gdp_fpgaii_top|clk_i | 11.112 8.845 | No paths - | No paths - | No paths - gdp_fpgaii_top|clk_i System | 11.112 9.357 | No paths - | No paths - | No paths - gdp_fpgaii_top|clk_i gdp_fpgaii_top|clk_i | 11.112 -1.961 | No paths - | No paths - | No paths - =================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: gdp_fpgaii_top|clk_i ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------- GDPHS.impl_key2\.kbd.PS2dec.p_lookup\.LookupData_1_0_0 gdp_fpgaii_top|clk_i PDP8KA DO7 LookupData[7] 6.020 -1.961 GDPHS.impl_key2\.kbd.PS2dec.p_lookup\.LookupData_1_0_0 gdp_fpgaii_top|clk_i PDP8KA DO6 LookupData[6] 5.999 -1.940 GDPHS.impl_key2\.kbd.PS2dec.p_lookup\.LookupData_1_0_0 gdp_fpgaii_top|clk_i PDP8KA DO5 LookupData[5] 5.995 -1.936 GDPHS.impl_key2\.kbd.PS2dec.p_lookup\.LookupData_1_0_0 gdp_fpgaii_top|clk_i PDP8KA DO0 LookupData[0] 5.954 -1.894 GDPHS.impl_key2\.kbd.PS2if.DataReg[3] gdp_fpgaii_top|clk_i FD1P3DX Q un1_kbd[3] 1.317 -1.067 GDPHS.impl_key2\.kbd.PS2if.DataReg[6] gdp_fpgaii_top|clk_i FD1P3DX Q un1_kbd[6] 1.309 -1.060 GDPHS.impl_key2\.kbd.PS2if.DataReg[4] gdp_fpgaii_top|clk_i FD1P3DX Q un1_kbd[4] 1.299 -1.050 GDPHS.impl_key2\.kbd.PS2if.DataReg[5] gdp_fpgaii_top|clk_i FD1P3DX Q un1_kbd[5] 1.297 -1.047 GDPHS.impl_key2\.kbd.PS2if.DataReg[0] gdp_fpgaii_top|clk_i FD1P3DX Q un1_kbd[0] 1.291 -0.985 GDPHS.impl_key2\.kbd.PS2dec.p_lookup\.LookupData_1_0_0 gdp_fpgaii_top|clk_i PDP8KA DO1 LookupData[1] 5.945 -0.966 ============================================================================================================================================ Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------- GDPHS.impl_key2\.kbd.PS2dec.p_lookup\.LookupData_1_0_0 gdp_fpgaii_top|clk_i PDP8KA ADR12 next_LookupAddress_23[8] 9.364 -1.961 GDPHS.impl_key2\.kbd.PS2dec.p_lookup\.LookupData_1_0_0 gdp_fpgaii_top|clk_i PDP8KA ADR10 next_LookupAddress_23[6] 9.364 -1.870 GDPHS.impl_key2\.kbd.PS2dec.p_lookup\.LookupData_1_0_0 gdp_fpgaii_top|clk_i PDP8KA ADR11 next_LookupAddress_23[7] 9.364 -1.870 GDPHS.impl_key2\.kbd.PS2dec.p_lookup\.LookupData_1_0_0 gdp_fpgaii_top|clk_i PDP8KA ADR8 next_LookupAddress_23[4] 9.364 -1.712 GDPHS.impl_key2\.kbd.PS2dec.p_lookup\.LookupData_1_0_0 gdp_fpgaii_top|clk_i PDP8KA ADR9 next_LookupAddress_23[5] 9.364 -1.712 GDPHS.impl_key2\.kbd.PS2dec.p_lookup\.LookupData_1_0_0 gdp_fpgaii_top|clk_i PDP8KA ADR6 next_LookupAddress_23[2] 9.364 -1.621 GDPHS.impl_key2\.kbd.PS2dec.p_lookup\.LookupData_1_0_0 gdp_fpgaii_top|clk_i PDP8KA ADR7 next_LookupAddress_23[3] 9.364 -1.621 GDPHS.GDP.vram.ram_address[14] gdp_fpgaii_top|clk_i FD1P3DX D N_111 10.400 -0.665 GDPHS.GDP.vram.ram_address[15] gdp_fpgaii_top|clk_i FD1P3DX D ram_address_RNO[15] 10.400 -0.665 GDPHS.impl_key2\.kbd.PS2dec.p_lookup\.LookupData_1_0_0 gdp_fpgaii_top|clk_i PDP8KA ADR5 next_LookupAddress_23[1] 9.364 -0.613 ========================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 11.112 - Setup time: 1.748 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.364 - Propagation time: 11.324 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.961 Number of logic level(s): 6 Starting point: GDPHS.impl_key2\.kbd.PS2dec.p_lookup\.LookupData_1_0_0 / DO7 Ending point: GDPHS.impl_key2\.kbd.PS2dec.p_lookup\.LookupData_1_0_0 / ADR12 The start point is clocked by gdp_fpgaii_top|clk_i [rising] on pin CLKR The end point is clocked by gdp_fpgaii_top|clk_i [rising] on pin CLKR Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------------- GDPHS.impl_key2\.kbd.PS2dec.p_lookup\.LookupData_1_0_0 PDP8KA DO7 Out 6.020 6.020 - LookupData[7] Net - - - - 13 GDPHS.impl_key2\.kbd.PS2dec.evaluate_RNIUL12 ORCALUT4 A In 0.000 6.020 - GDPHS.impl_key2\.kbd.PS2dec.evaluate_RNIUL12 ORCALUT4 Z Out 1.011 7.031 - nkccode_v_5_i_a2_0[3] Net - - - - 4 GDPHS.impl_key2\.kbd.PS2dec.next_LookupAddress_23_0_cry_4_0_RNO ORCALUT4 D In 0.000 7.031 - GDPHS.impl_key2\.kbd.PS2dec.next_LookupAddress_23_0_cry_4_0_RNO ORCALUT4 Z Out 0.829 7.860 - nkccode_v_5_m[3] Net - - - - 1 GDPHS.impl_key2\.kbd.PS2dec.next_LookupAddress_23_0_cry_4_0 CCU2 A0 In 0.000 7.860 - GDPHS.impl_key2\.kbd.PS2dec.next_LookupAddress_23_0_cry_4_0 CCU2 COUT1 Out 1.233 9.092 - next_LookupAddress_23_0_cry_5 Net - - - - 1 GDPHS.impl_key2\.kbd.PS2dec.next_LookupAddress_23_0_cry_6_0 CCU2 CIN In 0.000 9.092 - GDPHS.impl_key2\.kbd.PS2dec.next_LookupAddress_23_0_cry_6_0 CCU2 COUT1 Out 0.091 9.183 - next_LookupAddress_23_0_cry_7 Net - - - - 1 GDPHS.impl_key2\.kbd.PS2dec.next_LookupAddress_23_0_s_8_0 CCU2 CIN In 0.000 9.183 - GDPHS.impl_key2\.kbd.PS2dec.next_LookupAddress_23_0_s_8_0 CCU2 S0 Out 1.238 10.421 - next_LookupAddress_23_0_s_8_0_S0 Net - - - - 1 GDPHS.impl_key2\.kbd.PS2dec.next_LookupAddress_23[8] ORCALUT4 B In 0.000 10.421 - GDPHS.impl_key2\.kbd.PS2dec.next_LookupAddress_23[8] ORCALUT4 Z Out 0.903 11.324 - next_LookupAddress_23[8] Net - - - - 2 GDPHS.impl_key2\.kbd.PS2dec.p_lookup\.LookupData_1_0_0 PDP8KA ADR12 In 0.000 11.324 - =================================================================================================================================== Path information for path number 2: Requested Period: 11.112 - Setup time: 1.748 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.364 - Propagation time: 11.324 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.961 Number of logic level(s): 6 Starting point: GDPHS.impl_key2\.kbd.PS2dec.p_lookup\.LookupData_1_0_0 / DO7 Ending point: GDPHS.impl_key2\.kbd.PS2dec.p_lookup\.LookupData_1_0_0 / ADR12 The start point is clocked by gdp_fpgaii_top|clk_i [rising] on pin CLKR The end point is clocked by gdp_fpgaii_top|clk_i [rising] on pin CLKR Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------- GDPHS.impl_key2\.kbd.PS2dec.p_lookup\.LookupData_1_0_0 PDP8KA DO7 Out 6.020 6.020 - LookupData[7] Net - - - - 13 GDPHS.impl_key2\.kbd.PS2dec.evaluate_RNIUL12 ORCALUT4 A In 0.000 6.020 - GDPHS.impl_key2\.kbd.PS2dec.evaluate_RNIUL12 ORCALUT4 Z Out 1.011 7.031 - nkccode_v_5_i_a2_0[3] Net - - - - 4 GDPHS.impl_key2\.kbd.PS2dec.un1_nkccode_v_1_iv_a2[3] ORCALUT4 D In 0.000 7.031 - GDPHS.impl_key2\.kbd.PS2dec.un1_nkccode_v_1_iv_a2[3] ORCALUT4 Z Out 0.829 7.860 - un1_nkccode_v_1_iv_a2[3] Net - - - - 1 GDPHS.impl_key2\.kbd.PS2dec.next_LookupAddress_23_0_cry_4_0 CCU2 B1 In 0.000 7.860 - GDPHS.impl_key2\.kbd.PS2dec.next_LookupAddress_23_0_cry_4_0 CCU2 COUT1 Out 1.233 9.092 - next_LookupAddress_23_0_cry_5 Net - - - - 1 GDPHS.impl_key2\.kbd.PS2dec.next_LookupAddress_23_0_cry_6_0 CCU2 CIN In 0.000 9.092 - GDPHS.impl_key2\.kbd.PS2dec.next_LookupAddress_23_0_cry_6_0 CCU2 COUT1 Out 0.091 9.183 - next_LookupAddress_23_0_cry_7 Net - - - - 1 GDPHS.impl_key2\.kbd.PS2dec.next_LookupAddress_23_0_s_8_0 CCU2 CIN In 0.000 9.183 - GDPHS.impl_key2\.kbd.PS2dec.next_LookupAddress_23_0_s_8_0 CCU2 S0 Out 1.238 10.421 - next_LookupAddress_23_0_s_8_0_S0 Net - - - - 1 GDPHS.impl_key2\.kbd.PS2dec.next_LookupAddress_23[8] ORCALUT4 B In 0.000 10.421 - GDPHS.impl_key2\.kbd.PS2dec.next_LookupAddress_23[8] ORCALUT4 Z Out 0.903 11.324 - next_LookupAddress_23[8] Net - - - - 2 GDPHS.impl_key2\.kbd.PS2dec.p_lookup\.LookupData_1_0_0 PDP8KA ADR12 In 0.000 11.324 - =============================================================================================================================== Path information for path number 3: Requested Period: 11.112 - Setup time: 1.748 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.364 - Propagation time: 11.304 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.940 Number of logic level(s): 6 Starting point: GDPHS.impl_key2\.kbd.PS2dec.p_lookup\.LookupData_1_0_0 / DO6 Ending point: GDPHS.impl_key2\.kbd.PS2dec.p_lookup\.LookupData_1_0_0 / ADR12 The start point is clocked by gdp_fpgaii_top|clk_i [rising] on pin CLKR The end point is clocked by gdp_fpgaii_top|clk_i [rising] on pin CLKR Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------------- GDPHS.impl_key2\.kbd.PS2dec.p_lookup\.LookupData_1_0_0 PDP8KA DO6 Out 5.999 5.999 - LookupData[6] Net - - - - 10 GDPHS.impl_key2\.kbd.PS2dec.p_lookup\.LookupData_1_0_0_RNIEVL1 ORCALUT4 B In 0.000 5.999 - GDPHS.impl_key2\.kbd.PS2dec.p_lookup\.LookupData_1_0_0_RNIEVL1 ORCALUT4 Z Out 1.011 7.010 - N_1012 Net - - - - 4 GDPHS.impl_key2\.kbd.PS2dec.next_LookupAddress_23_0_cry_4_0_RNO ORCALUT4 A In 0.000 7.010 - GDPHS.impl_key2\.kbd.PS2dec.next_LookupAddress_23_0_cry_4_0_RNO ORCALUT4 Z Out 0.829 7.839 - nkccode_v_5_m[3] Net - - - - 1 GDPHS.impl_key2\.kbd.PS2dec.next_LookupAddress_23_0_cry_4_0 CCU2 A0 In 0.000 7.839 - GDPHS.impl_key2\.kbd.PS2dec.next_LookupAddress_23_0_cry_4_0 CCU2 COUT1 Out 1.233 9.072 - next_LookupAddress_23_0_cry_5 Net - - - - 1 GDPHS.impl_key2\.kbd.PS2dec.next_LookupAddress_23_0_cry_6_0 CCU2 CIN In 0.000 9.072 - GDPHS.impl_key2\.kbd.PS2dec.next_LookupAddress_23_0_cry_6_0 CCU2 COUT1 Out 0.091 9.162 - next_LookupAddress_23_0_cry_7 Net - - - - 1 GDPHS.impl_key2\.kbd.PS2dec.next_LookupAddress_23_0_s_8_0 CCU2 CIN In 0.000 9.162 - GDPHS.impl_key2\.kbd.PS2dec.next_LookupAddress_23_0_s_8_0 CCU2 S0 Out 1.238 10.400 - next_LookupAddress_23_0_s_8_0_S0 Net - - - - 1 GDPHS.impl_key2\.kbd.PS2dec.next_LookupAddress_23[8] ORCALUT4 B In 0.000 10.400 - GDPHS.impl_key2\.kbd.PS2dec.next_LookupAddress_23[8] ORCALUT4 Z Out 0.903 11.304 - next_LookupAddress_23[8] Net - - - - 2 GDPHS.impl_key2\.kbd.PS2dec.p_lookup\.LookupData_1_0_0 PDP8KA ADR12 In 0.000 11.304 - =================================================================================================================================== Path information for path number 4: Requested Period: 11.112 - Setup time: 1.748 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.364 - Propagation time: 11.304 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.940 Number of logic level(s): 6 Starting point: GDPHS.impl_key2\.kbd.PS2dec.p_lookup\.LookupData_1_0_0 / DO6 Ending point: GDPHS.impl_key2\.kbd.PS2dec.p_lookup\.LookupData_1_0_0 / ADR12 The start point is clocked by gdp_fpgaii_top|clk_i [rising] on pin CLKR The end point is clocked by gdp_fpgaii_top|clk_i [rising] on pin CLKR Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------- GDPHS.impl_key2\.kbd.PS2dec.p_lookup\.LookupData_1_0_0 PDP8KA DO6 Out 5.999 5.999 - LookupData[6] Net - - - - 10 GDPHS.impl_key2\.kbd.PS2dec.p_lookup\.LookupData_1_0_0_RNIEVL1 ORCALUT4 B In 0.000 5.999 - GDPHS.impl_key2\.kbd.PS2dec.p_lookup\.LookupData_1_0_0_RNIEVL1 ORCALUT4 Z Out 1.011 7.010 - N_1012 Net - - - - 4 GDPHS.impl_key2\.kbd.PS2dec.un1_nkccode_v_1_iv_a2[3] ORCALUT4 A In 0.000 7.010 - GDPHS.impl_key2\.kbd.PS2dec.un1_nkccode_v_1_iv_a2[3] ORCALUT4 Z Out 0.829 7.839 - un1_nkccode_v_1_iv_a2[3] Net - - - - 1 GDPHS.impl_key2\.kbd.PS2dec.next_LookupAddress_23_0_cry_4_0 CCU2 B1 In 0.000 7.839 - GDPHS.impl_key2\.kbd.PS2dec.next_LookupAddress_23_0_cry_4_0 CCU2 COUT1 Out 1.233 9.072 - next_LookupAddress_23_0_cry_5 Net - - - - 1 GDPHS.impl_key2\.kbd.PS2dec.next_LookupAddress_23_0_cry_6_0 CCU2 CIN In 0.000 9.072 - GDPHS.impl_key2\.kbd.PS2dec.next_LookupAddress_23_0_cry_6_0 CCU2 COUT1 Out 0.091 9.162 - next_LookupAddress_23_0_cry_7 Net - - - - 1 GDPHS.impl_key2\.kbd.PS2dec.next_LookupAddress_23_0_s_8_0 CCU2 CIN In 0.000 9.162 - GDPHS.impl_key2\.kbd.PS2dec.next_LookupAddress_23_0_s_8_0 CCU2 S0 Out 1.238 10.400 - next_LookupAddress_23_0_s_8_0_S0 Net - - - - 1 GDPHS.impl_key2\.kbd.PS2dec.next_LookupAddress_23[8] ORCALUT4 B In 0.000 10.400 - GDPHS.impl_key2\.kbd.PS2dec.next_LookupAddress_23[8] ORCALUT4 Z Out 0.903 11.304 - next_LookupAddress_23[8] Net - - - - 2 GDPHS.impl_key2\.kbd.PS2dec.p_lookup\.LookupData_1_0_0 PDP8KA ADR12 In 0.000 11.304 - ================================================================================================================================== Path information for path number 5: Requested Period: 11.112 - Setup time: 1.748 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.364 - Propagation time: 11.300 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.936 Number of logic level(s): 6 Starting point: GDPHS.impl_key2\.kbd.PS2dec.p_lookup\.LookupData_1_0_0 / DO5 Ending point: GDPHS.impl_key2\.kbd.PS2dec.p_lookup\.LookupData_1_0_0 / ADR12 The start point is clocked by gdp_fpgaii_top|clk_i [rising] on pin CLKR The end point is clocked by gdp_fpgaii_top|clk_i [rising] on pin CLKR Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------------- GDPHS.impl_key2\.kbd.PS2dec.p_lookup\.LookupData_1_0_0 PDP8KA DO5 Out 5.995 5.995 - LookupData[5] Net - - - - 9 GDPHS.impl_key2\.kbd.PS2dec.p_lookup\.LookupData_1_0_0_RNIEVL1 ORCALUT4 A In 0.000 5.995 - GDPHS.impl_key2\.kbd.PS2dec.p_lookup\.LookupData_1_0_0_RNIEVL1 ORCALUT4 Z Out 1.011 7.006 - N_1012 Net - - - - 4 GDPHS.impl_key2\.kbd.PS2dec.next_LookupAddress_23_0_cry_4_0_RNO ORCALUT4 A In 0.000 7.006 - GDPHS.impl_key2\.kbd.PS2dec.next_LookupAddress_23_0_cry_4_0_RNO ORCALUT4 Z Out 0.829 7.835 - nkccode_v_5_m[3] Net - - - - 1 GDPHS.impl_key2\.kbd.PS2dec.next_LookupAddress_23_0_cry_4_0 CCU2 A0 In 0.000 7.835 - GDPHS.impl_key2\.kbd.PS2dec.next_LookupAddress_23_0_cry_4_0 CCU2 COUT1 Out 1.233 9.068 - next_LookupAddress_23_0_cry_5 Net - - - - 1 GDPHS.impl_key2\.kbd.PS2dec.next_LookupAddress_23_0_cry_6_0 CCU2 CIN In 0.000 9.068 - GDPHS.impl_key2\.kbd.PS2dec.next_LookupAddress_23_0_cry_6_0 CCU2 COUT1 Out 0.091 9.158 - next_LookupAddress_23_0_cry_7 Net - - - - 1 GDPHS.impl_key2\.kbd.PS2dec.next_LookupAddress_23_0_s_8_0 CCU2 CIN In 0.000 9.158 - GDPHS.impl_key2\.kbd.PS2dec.next_LookupAddress_23_0_s_8_0 CCU2 S0 Out 1.238 10.396 - next_LookupAddress_23_0_s_8_0_S0 Net - - - - 1 GDPHS.impl_key2\.kbd.PS2dec.next_LookupAddress_23[8] ORCALUT4 B In 0.000 10.396 - GDPHS.impl_key2\.kbd.PS2dec.next_LookupAddress_23[8] ORCALUT4 Z Out 0.903 11.300 - next_LookupAddress_23[8] Net - - - - 2 GDPHS.impl_key2\.kbd.PS2dec.p_lookup\.LookupData_1_0_0 PDP8KA ADR12 In 0.000 11.300 - =================================================================================================================================== ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------- GDPHS.impl_key2\.kbd.PS2FiFo.AND2_t3 System AND2 Z rden_i 0.000 -0.088 GDPHS.impl_key2\.kbd.PS2FiFo.AND2_t4 System AND2 Z wren_i 0.000 -0.088 GDPHS.impl_key2\.kbd.PS2FiFo.e_cmp_0 System ALEB2 LE co0_1 0.000 0.501 GDPHS.impl_key2\.kbd.PS2FiFo.g_cmp_0 System AGEB2 GE co0_2 0.000 0.501 GDPHS.impl_key2\.kbd.PS2FiFo.e_cmp_1 System ALEB2 LE cmp_le_1_c 0.000 8.845 GDPHS.impl_key2\.kbd.PS2FiFo.g_cmp_1 System AGEB2 GE cmp_ge_d1 0.000 10.083 GDPHS.impl_key2\.kbd.PS2FiFo.XOR2_t1 System XOR2 Z fcnt_en 0.000 10.975 GDPHS.impl_key2\.kbd.PS2FiFo.AND2_t0 System AND2 Z dec_wre3 0.000 11.112 ========================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------- GDPHS.impl_key2\.kbd.PS2FiFo.AND2_t2 System AND2 B rden_i_inv 0.501 -0.088 GDPHS.impl_key2\.kbd.PS2FiFo.g_cmp_1 System AGEB2 B0 wren_i_inv 0.501 -0.088 GDPHS.impl_key2\.kbd.PS2FiFo.AND2_t0 System AND2 B wren_i 0.501 0.501 GDPHS.impl_key2\.kbd.PS2FiFo.AND2_t2 System AND2 A wren_i 0.501 0.501 GDPHS.impl_key2\.kbd.PS2FiFo.XOR2_t1 System XOR2 A wren_i 0.501 0.501 GDPHS.impl_key2\.kbd.PS2FiFo.XOR2_t1 System XOR2 B rden_i 0.501 0.501 GDPHS.impl_key2\.kbd.PS2FiFo.e_cmp_0 System ALEB2 B0 rden_i 0.501 0.501 GDPHS.impl_key2\.kbd.PS2FiFo.e_cmp_1 System ALEB2 CI co0_1 0.501 0.501 GDPHS.impl_key2\.kbd.PS2FiFo.g_cmp_0 System AGEB2 B0 wren_i 0.501 0.501 GDPHS.impl_key2\.kbd.PS2FiFo.g_cmp_0 System AGEB2 B1 wren_i 0.501 0.501 =========================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 0.501 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 0.501 - Propagation time: 0.589 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -0.088 Number of logic level(s): 1 Starting point: GDPHS.impl_key2\.kbd.PS2FiFo.AND2_t3 / Z Ending point: GDPHS.impl_key2\.kbd.PS2FiFo.AND2_t2 / B The start point is clocked by System [rising] The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------- GDPHS.impl_key2\.kbd.PS2FiFo.AND2_t3 AND2 Z Out 0.000 0.000 - rden_i Net - - - - 14 GDPHS.impl_key2\.kbd.PS2FiFo.INV_1 INV A In 0.000 0.000 - GDPHS.impl_key2\.kbd.PS2FiFo.INV_1 INV Z Out 0.589 0.589 - rden_i_inv Net - - - - 1 GDPHS.impl_key2\.kbd.PS2FiFo.AND2_t2 AND2 B In 0.000 0.589 - =================================================================================================== Path information for path number 2: Requested Period: 0.501 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 0.501 - Propagation time: 0.589 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -0.088 Number of logic level(s): 1 Starting point: GDPHS.impl_key2\.kbd.PS2FiFo.AND2_t4 / Z Ending point: GDPHS.impl_key2\.kbd.PS2FiFo.g_cmp_1 / B0 The start point is clocked by System [rising] The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------- GDPHS.impl_key2\.kbd.PS2FiFo.AND2_t4 AND2 Z Out 0.000 0.000 - wren_i Net - - - - 9 GDPHS.impl_key2\.kbd.PS2FiFo.INV_0 INV A In 0.000 0.000 - GDPHS.impl_key2\.kbd.PS2FiFo.INV_0 INV Z Out 0.589 0.589 - wren_i_inv Net - - - - 1 GDPHS.impl_key2\.kbd.PS2FiFo.g_cmp_1 AGEB2 B0 In 0.000 0.589 - ==================================================================================================== Path information for path number 3: Requested Period: 0.501 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 0.501 - Propagation time: 0.000 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 0.501 Number of logic level(s): 0 Starting point: GDPHS.impl_key2\.kbd.PS2FiFo.e_cmp_0 / LE Ending point: GDPHS.impl_key2\.kbd.PS2FiFo.e_cmp_1 / CI The start point is clocked by System [rising] The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------- GDPHS.impl_key2\.kbd.PS2FiFo.e_cmp_0 ALEB2 LE Out 0.000 0.000 - co0_1 Net - - - - 1 GDPHS.impl_key2\.kbd.PS2FiFo.e_cmp_1 ALEB2 CI In 0.000 0.000 - ==================================================================================================== Path information for path number 4: Requested Period: 0.501 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 0.501 - Propagation time: 0.000 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 0.501 Number of logic level(s): 0 Starting point: GDPHS.impl_key2\.kbd.PS2FiFo.g_cmp_0 / GE Ending point: GDPHS.impl_key2\.kbd.PS2FiFo.g_cmp_1 / CI The start point is clocked by System [rising] The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------- GDPHS.impl_key2\.kbd.PS2FiFo.g_cmp_0 AGEB2 GE Out 0.000 0.000 - co0_2 Net - - - - 1 GDPHS.impl_key2\.kbd.PS2FiFo.g_cmp_1 AGEB2 CI In 0.000 0.000 - ==================================================================================================== Path information for path number 5: Requested Period: 0.501 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 0.501 - Propagation time: 0.000 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 0.501 Number of logic level(s): 0 Starting point: GDPHS.impl_key2\.kbd.PS2FiFo.AND2_t3 / Z Ending point: GDPHS.impl_key2\.kbd.PS2FiFo.e_cmp_0 / B0 The start point is clocked by System [rising] The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------- GDPHS.impl_key2\.kbd.PS2FiFo.AND2_t3 AND2 Z Out 0.000 0.000 - rden_i Net - - - - 14 GDPHS.impl_key2\.kbd.PS2FiFo.e_cmp_0 ALEB2 B0 In 0.000 0.000 - ==================================================================================================== ##### END OF TIMING REPORT #####] --------------------------------------- Resource Usage Report Part: lfxp6c-5 Register bits: 1461 of 5760 (25%) Latch bits: 16 PIC Latch: 16 I/O cells: 140 Block Rams : 2 of 10 (20%) Details: AND2: 4 BB: 52 CB2: 2 CCU2: 304 CU2: 2 DPR16X2B: 4 FADD2: 1 FD1P3AX: 24 FD1P3BX: 94 FD1P3DX: 860 FD1P3IX: 4 FD1S3AX: 49 FD1S3BX: 49 FD1S3DX: 317 FD1S3IX: 18 FD1S3JX: 1 GSR: 1 IB: 32 IFS1P3BX: 3 IFS1P3DX: 3 IFS1S1B: 16 INV: 35 L6MUX21: 31 OB: 55 OBZ: 1 OFS1P3BX: 26 OFS1P3DX: 4 OFS1P3IX: 9 ORCALUT4: 2587 PDP8KA: 1 PFUMX: 111 PUR: 1 ROM16X1: 2 SP8KA: 1 VHI: 1 VLO: 1 XOR2: 1 false: 35 true: 35 Mapper successful! At Mapper Exit (Time elapsed 0h:00m:32s; Memory used current: 57MB peak: 230MB) Process took 0h:00m:32s realtime, 0h:00m:32s cputime # Fri Oct 10 21:52:00 2014 ###########################################################]